[PATCH] [binutils][arm] Fix disassembly of conditional VDUPs
Fredrik Strupe
fredrik@strupe.net
Sat Mar 14 14:10:43 GMT 2020
On 12.03.2020 15:32, Richard Earnshaw wrote:
>> VDUP (neon) instructions can be conditional, but this is not taken into
>> account in the current master. This commit fixes that by i) fixing the
>> VDUP instruction masks and ii) adding logic for disassembling
>> conditional neon instructions.
>>
>
> Thanks for posting this. I've a few comments inlined below,
Thanks for the feedback. I've updated the patch with the requested changes.
> but before progressing further, I think this will need a copyright assignment before it can go in. Do you already have one in place?
>
I don't. How does that work?
>> for (insn = neon_opcodes; insn->assembler; insn++)
>> {
>> - if ((given & insn->mask) == insn->value)
>> + unsigned long cond_mask = insn->mask;
>> + unsigned long cond_value = insn->value;
>> + int cond;
>> +
>> + if (thumb)
>> + {
>> + cond_mask |= 0xf0000000;
>> + cond_value |= 0xe0000000;
>
> This feels fragile, and while it is probably a NOP for the unconditional neon instructions, it /feels/ wrong to write it this way. Instead I think you should only do this for the instructions that are conditional (ie have ((cond_mask & 0xf0000000) == 0)).
>
Agreed. I've added a check for that.
> Some comments through this code would also help. It's far from clear what the manipulations are for.
>
Comments added.
>> + if ((given & cond_mask) == cond_value)
>> {
>> signed long value_in_comment = 0;
>> bfd_boolean is_unpredictable = FALSE;
>> const char *c;
>> -
>
> Don't remove single blank lines between variable declarations and code blocks.
>
Sorry, that was not intentional.
>
> Finally, you're also missing some test cases for the testsuite.
>
I've added a few tests at what I believe should be the right place. I think however that those tests will fail if run on a system that doesn't support neon instructions (because of the -mfpu=neon flag to as). Is there a way to skip the tests in such cases?
Fredrik
---
VDUP (neon) instructions can be conditional, but this is not taken into
account in the current master. This commit fixes that by i) fixing the
VDUP instruction masks and ii) adding logic for disassembling
conditional neon instructions.
A couple of new tests have also been added.
opcodes/ChangeLog:
2020-03-14 Fredrik Strupe <fredrik@strupe.net>
* arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
(print_insn_neon): Support disassembly of conditional
instructions.
binutils/ChangeLog:
2020-03-14 Fredrik Strupe <fredrik@strupe.net>
* testsuite/binutils-all/arm/vdup-cond.d: New test for testing that
conditional VDUP instructions are disassembled correctly.
* testsuite/binutils-all/arm/vdup-cond.s: New file used by
vdup-cond.d.
* testsuite/binutils-all/arm/vdup-thumb.d: New test for testing that
VDUP instructions (which are conditional in A32) can be disassembled in
thumb mode.
* testsuite/binutils-all/arm/vdup-cond.s: New file used by
vdup-thumb.d.
---
.../testsuite/binutils-all/arm/vdup-cond.d | 27 +++++++++
.../testsuite/binutils-all/arm/vdup-cond.s | 18 ++++++
.../testsuite/binutils-all/arm/vdup-thumb.d | 13 +++++
.../testsuite/binutils-all/arm/vdup-thumb.s | 4 ++
opcodes/arm-dis.c | 55 ++++++++++++++++---
5 files changed, 108 insertions(+), 9 deletions(-)
create mode 100644 binutils/testsuite/binutils-all/arm/vdup-cond.d
create mode 100644 binutils/testsuite/binutils-all/arm/vdup-cond.s
create mode 100644 binutils/testsuite/binutils-all/arm/vdup-thumb.d
create mode 100644 binutils/testsuite/binutils-all/arm/vdup-thumb.s
diff --git a/binutils/testsuite/binutils-all/arm/vdup-cond.d b/binutils/testsuite/binutils-all/arm/vdup-cond.d
new file mode 100644
index 0000000000..f75931b466
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/vdup-cond.d
@@ -0,0 +1,27 @@
+#PROG: objcopy
+#source vdup-cond.s
+#as: -mfpu=neon
+#objdump: -d
+#skip: *-*-pe *-wince-* *-*-coff
+#name: Check if disassembler can handle conditional neon (vdup) instructions
+
+.*: +file format .*arm.*
+
+Disassembly of section \.vdups:
+
+.+ <\.vdups>:
+[^:]+: 0e800b10 vdupeq.32 d0, r0
+[^:]+: 1e800b10 vdupne.32 d0, r0
+[^:]+: 2e800b10 vdupcs.32 d0, r0
+[^:]+: 3e800b10 vdupcc.32 d0, r0
+[^:]+: 4e800b10 vdupmi.32 d0, r0
+[^:]+: 5e800b10 vduppl.32 d0, r0
+[^:]+: 6e800b10 vdupvs.32 d0, r0
+[^:]+: 7e800b10 vdupvc.32 d0, r0
+[^:]+: 8e800b10 vduphi.32 d0, r0
+[^:]+: 9e800b10 vdupls.32 d0, r0
+[^:]+: ae800b10 vdupge.32 d0, r0
+[^:]+: be800b10 vduplt.32 d0, r0
+[^:]+: ce800b10 vdupgt.32 d0, r0
+[^:]+: de800b10 vduple.32 d0, r0
+[^:]+: ee800b10 vdup.32 d0, r0
diff --git a/binutils/testsuite/binutils-all/arm/vdup-cond.s b/binutils/testsuite/binutils-all/arm/vdup-cond.s
new file mode 100644
index 0000000000..cc544ef29c
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/vdup-cond.s
@@ -0,0 +1,18 @@
+.text
+.arm
+.section .vdups, "ax"
+vdupeq.32 d0, r0
+vdupne.32 d0, r0
+vdupcs.32 d0, r0
+vdupcc.32 d0, r0
+vdupmi.32 d0, r0
+vduppl.32 d0, r0
+vdupvs.32 d0, r0
+vdupvc.32 d0, r0
+vduphi.32 d0, r0
+vdupls.32 d0, r0
+vdupge.32 d0, r0
+vduplt.32 d0, r0
+vdupgt.32 d0, r0
+vduple.32 d0, r0
+vdup.32 d0, r0
diff --git a/binutils/testsuite/binutils-all/arm/vdup-thumb.d b/binutils/testsuite/binutils-all/arm/vdup-thumb.d
new file mode 100644
index 0000000000..30e80340f6
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/vdup-thumb.d
@@ -0,0 +1,13 @@
+#PROG: objcopy
+#source vdup-cond.s
+#as: -mfpu=neon
+#objdump: -d
+#skip: *-*-pe *-wince-* *-*-coff
+#name: Check if disassembler can handle vdup instructions in thumb
+
+.*: +file format .*arm.*
+
+Disassembly of section \.vdups:
+
+.+ <\.vdups>:
+[^:]+: ee80 0b10 vdup.32 d0, r0
diff --git a/binutils/testsuite/binutils-all/arm/vdup-thumb.s b/binutils/testsuite/binutils-all/arm/vdup-thumb.s
new file mode 100644
index 0000000000..d98b6a41ea
--- /dev/null
+++ b/binutils/testsuite/binutils-all/arm/vdup-thumb.s
@@ -0,0 +1,4 @@
+.text
+.thumb
+.section .vdups, "ax"
+vdup.32 d0, r0
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index b926b65d6a..83f9869e4d 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1494,17 +1494,17 @@ static const struct opcode32 neon_opcodes[] =
/* Data transfer between ARM and NEON registers. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
+ 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
+ 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
+ 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
+ 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
+ 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
+ 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
/* Move data element to all lanes. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
@@ -9038,7 +9038,45 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
for (insn = neon_opcodes; insn->assembler; insn++)
{
- if ((given & insn->mask) == insn->value)
+ unsigned long cond_mask = insn->mask;
+ unsigned long cond_value = insn->value;
+ int cond;
+
+ if (thumb)
+ {
+ if ((cond_mask & 0xf0000000) == 0) {
+ /* For the entries in neon_opcodes, an opcode mask/value with
+ the high 4 bits equal to 0 indicates a conditional
+ instruction. For thumb however, we need to include those
+ bits in the instruction matching. */
+ cond_mask |= 0xf0000000;
+ /* Furthermore, the thumb encoding of a conditional instruction
+ will have the high 4 bits equal to 0xe. */
+ cond_value |= 0xe0000000;
+ }
+ if (ifthen_state)
+ cond = IFTHEN_COND;
+ else
+ cond = COND_UNCOND;
+ }
+ else
+ {
+ if ((given & 0xf0000000) == 0xf0000000)
+ {
+ /* If the instruction is unconditional, update the mask to only
+ match against unconditional opcode values. */
+ cond_mask |= 0xf0000000;
+ cond = COND_UNCOND;
+ }
+ else
+ {
+ cond = (given >> 28) & 0xf;
+ if (cond == 0xe)
+ cond = COND_UNCOND;
+ }
+ }
+
+ if ((given & cond_mask) == cond_value)
{
signed long value_in_comment = 0;
bfd_boolean is_unpredictable = FALSE;
@@ -9060,8 +9098,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
/* Fall through. */
case 'c':
- if (thumb && ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
+ func (stream, "%s", arm_conditional[cond]);
break;
case 'A':
--
2.20.1
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