[PATCH] [binutils][arm] Fix disassembly of conditional VDUPs
Fredrik Strupe
fredrik@strupe.net
Sun Mar 8 13:48:51 GMT 2020
VDUP (neon) instructions can be conditional, but this is not taken into
account in the current master. This commit fixes that by i) fixing the
VDUP instruction masks and ii) adding logic for disassembling
conditional neon instructions.
Before patch:
$ objdump -b binary -m arm -D vdups.bin
...
00000000 <.data>:
0: 0e800b10 vdup.32 d0, r0
4: 1e800b10 ; <UNDEFINED> instruction: 0x1e800b10
8: 2e800b10 vdup.32 d0, r0
c: 3e800b10 ; <UNDEFINED> instruction: 0x3e800b10
10: 4e800b10 vdup.32 d0, r0
14: 5e800b10 ; <UNDEFINED> instruction: 0x5e800b10
18: 6e800b10 vdup.32 d0, r0
1c: 7e800b10 ; <UNDEFINED> instruction: 0x7e800b10
20: 8e800b10 vdup.32 d0, r0
24: 9e800b10 ; <UNDEFINED> instruction: 0x9e800b10
28: ae800b10 vdup.32 d0, r0
2c: be800b10 ; <UNDEFINED> instruction: 0xbe800b10
30: ce800b10 vdup.32 d0, r0
34: de800b10 ; <UNDEFINED> instruction: 0xde800b10
38: ee800b10 vdup.32 d0, r0
After patch:
00000000 <.data>:
0: 0e800b10 vdupeq.32 d0, r0
4: 1e800b10 vdupne.32 d0, r0
8: 2e800b10 vdupcs.32 d0, r0
c: 3e800b10 vdupcc.32 d0, r0
10: 4e800b10 vdupmi.32 d0, r0
14: 5e800b10 vduppl.32 d0, r0
18: 6e800b10 vdupvs.32 d0, r0
1c: 7e800b10 vdupvc.32 d0, r0
20: 8e800b10 vduphi.32 d0, r0
24: 9e800b10 vdupls.32 d0, r0
28: ae800b10 vdupge.32 d0, r0
2c: be800b10 vduplt.32 d0, r0
30: ce800b10 vdupgt.32 d0, r0
34: de800b10 vduple.32 d0, r0
38: ee800b10 vdup.32 d0, r0
opcodes/ChangeLog:
2020-03-08 Fredrik Strupe <fredrik@strupe.net>
* arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
(print_insn_neon): Support disassembly of conditional
instructions.
---
opcodes/arm-dis.c | 46 ++++++++++++++++++++++++++++++++++++----------
1 file changed, 36 insertions(+), 10 deletions(-)
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index b926b65d6a..709443fcf5 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1494,17 +1494,17 @@ static const struct opcode32 neon_opcodes[] =
/* Data transfer between ARM and NEON registers. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
+ 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
+ 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
+ 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
+ 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
+ 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
+ 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
/* Move data element to all lanes. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
@@ -9038,12 +9038,39 @@ print_insn_neon (struct disassemble_info *info,
long given, bfd_boolean thumb)
for (insn = neon_opcodes; insn->assembler; insn++)
{
- if ((given & insn->mask) == insn->value)
+ unsigned long cond_mask = insn->mask;
+ unsigned long cond_value = insn->value;
+ int cond;
+
+ if (thumb)
+ {
+ cond_mask |= 0xf0000000;
+ cond_value |= 0xe0000000;
+ if (ifthen_state)
+ cond = IFTHEN_COND;
+ else
+ cond = COND_UNCOND;
+ }
+ else
+ {
+ if ((given & 0xf0000000) == 0xf0000000)
+ {
+ cond_mask |= 0xf0000000;
+ cond = COND_UNCOND;
+ }
+ else
+ {
+ cond = (given >> 28) & 0xf;
+ if (cond == 0xe)
+ cond = COND_UNCOND;
+ }
+ }
+
+ if ((given & cond_mask) == cond_value)
{
signed long value_in_comment = 0;
bfd_boolean is_unpredictable = FALSE;
const char *c;
-
for (c = insn->assembler; *c; c++)
{
if (*c == '%')
@@ -9060,8 +9087,7 @@ print_insn_neon (struct disassemble_info *info,
long given, bfd_boolean thumb)
/* Fall through. */
case 'c':
- if (thumb && ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
+ func (stream, "%s", arm_conditional[cond]);
break;
case 'A':
--
2.20.1
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