x86: Add support for Intel AMX instructions

[H.J. Lu]

On Tue, Jun 30, 2020 at 9:32 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 30.06.2020 14:26, H.J. Lu wrote:
> > On Mon, Jun 29, 2020 at 11:29 PM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 28.06.2020 09:43, Cui, Lili via Binutils wrote:
> >>> @@ -3153,6 +3201,16 @@ static const char *att_names_zmm[] = {
> >>>    "%zmm28", "%zmm29", "%zmm30", "%zmm31"
> >>>  };
> >>>
> >>> +static const char **names_tmm;
> >>> +static const char *intel_names_tmm[] = {
> >>> +  "tmm0", "tmm1", "tmm2", "tmm3",
> >>> +  "tmm4", "tmm5", "tmm6", "tmm7"
> >>> +};
> >>> +static const char *att_names_tmm[] = {
> >>> +  "%tmm0", "%tmm1", "%tmm2", "%tmm3",
> >>> +  "%tmm4", "%tmm5", "%tmm6", "%tmm7"
> >>> +};
> >>
> >> Upon further consideration I don't think this and ...
> >>
> >>> --- a/opcodes/i386-reg.tbl
> >>> +++ b/opcodes/i386-reg.tbl
> >>> @@ -278,6 +278,15 @@ zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
> >>>  zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
> >>>  zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
> >>>  zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
> >>> +// TMM registers for AMX
> >>> +tmm0, Class=RegSIMD|Tmmword, 0, 0, Dw2Inval, Dw2Inval
> >>> +tmm1, Class=RegSIMD|Tmmword, 0, 1, Dw2Inval, Dw2Inval
> >>> +tmm2, Class=RegSIMD|Tmmword, 0, 2, Dw2Inval, Dw2Inval
> >>> +tmm3, Class=RegSIMD|Tmmword, 0, 3, Dw2Inval, Dw2Inval
> >>> +tmm4, Class=RegSIMD|Tmmword, 0, 4, Dw2Inval, Dw2Inval
> >>> +tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval
> >>> +tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
> >>> +tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
> >>
> >> ... this is quite sufficient: How many registers there are depends on
> >> the selected palette, and I don't think gas should needlessly restrict
> >> encoding options. The disassembler needs to handle the high bits of
> >> the register encoding fields in any event - whether by properly
> >> decoding the high bits or by properly considering the encodings as
> >> (bad) is secondary there (but should of course be in line with the
> >> choice on the assembler side).
> >>
> >
> > Disassembler should check the high bits of the register encoding fields.
> > But i386-reg.tbl is used by assembler.   I don't see anything wrong with
> > tmm in i386-reg.tbl.
>
> The specification does not restrict %tmm to 0-7; it's merely
> palette 1 which does (and the tilecfg register is nothing the
> assembler can know the state of). The assembler imo should
> support all 16 encodable registers right away. And of course
> the disassembler then should follow suit.
>

Sounds reasonable.   Lili, please add tmm8-15.

-- 
H.J.