x86: Add support for Intel AMX instructions

[H.J. Lu]

On Tue, Jun 30, 2020 at 2:33 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 30.06.2020 11:12, Cui, Lili wrote:
> >> On Mon, Jun 29, 2020 at 7:48 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>
> >>> On 29.06.2020 14:46, H.J. Lu wrote:
> >>>> On Mon, Jun 29, 2020 at 3:03 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>>>> On 28.06.2020 09:43, Cui, Lili via Binutils wrote:
> >>>>>> --- /dev/null
> >>>>>> +++ b/gas/testsuite/gas/i386/x86-64-amx-intel.d
> >>>>>> @@ -0,0 +1,69 @@
> >>>>>> +#as:
> >>>>>> +#objdump: -d -Mintel
> >>>>>> +#name: x86_64 AMX insns in Intel syntax
> >>>>>> +#source: x86-64-amx.s
> >>>>>> +
> >>>>>> +.*: +file format .*
> >>>>>> +
> >>>>>> +
> >>>>>> +Disassembly of section \.text:
> >>>>>> +
> >>>>>> +0+ <_start>:
> >>>>>> +[    ]*[a-f0-9]+:[   ]*c4 e2 78 49 04 51[    ]*ldtilecfg \[rcx\+rdx\*2\]
> >>>>>> +[    ]*[a-f0-9]+:[   ]*c4 e2 79 49 04 51[    ]*sttilecfg \[rcx\+rdx\*2\]
> >>>>>> +[    ]*[a-f0-9]+:[   ]*c4 e2 52 5c dc[       ]*tdpbf16ps tmm3,tmm4,tmm5
> >>>>>> +[    ]*[a-f0-9]+:[   ]*c4 e2 63 5e ca[       ]*tdpbssd tmm1,tmm2,tmm3
> >>>>>> +[    ]*[a-f0-9]+:[   ]*c4 e2 62 5e ca[       ]*tdpbsud tmm1,tmm2,tmm3
> >>>>>> +[    ]*[a-f0-9]+:[   ]*c4 e2 61 5e ca[       ]*tdpbusd tmm1,tmm2,tmm3
> >>>>>> +[    ]*[a-f0-9]+:[   ]*c4 e2 60 5e ca[       ]*tdpbuud tmm1,tmm2,tmm3
> >>>>>> +[    ]*[a-f0-9]+:[   ]*c4 e2 7b 4b 2c 25 00[         ]*tileloadd tmm5,ds:0x0
> >>>>>> +[    ]*[a-f0-9]+:[   ]*00 00 00[     ]*
> >>>>>> +[    ]*[a-f0-9]+:[   ]*c4 e2 7b 4b 2c 21[    ]*tileloadd tmm5,\[rcx\+riz\*1\]
> >>>>>> +[    ]*[a-f0-9]+:[   ]*67 c4 e2 7b 4b 2c 21[         ]*tileloadd
> >> tmm5,\[ecx\+eiz\*1\]
> >>>>>> +[    ]*[a-f0-9]+:[   ]*c4 e2 7b 4b 2c 11[    ]*tileloadd tmm5,\[rcx\+rdx\*1\]
> >>>>>> +[    ]*[a-f0-9]+:[   ]*67 c4 e2 7b 4b 0c 51[         ]*tileloadd
> >> tmm1,\[ecx\+edx\*2\]
> >>>>>
> >>>>> Is this (not very intuitive) representation agreed with Microsoft's
> >>>>> MASM team? I ask because I'd prefer it to be visually recognizable
> >>>>> that the effective address is _not_ [<base>+<index>*<scale>] here.
> >>>>> The form I'm planning to use in my own disassembler (at least until
> >>>>> knowing otherwise for MASM) is [<base>+<index>*<scale>n] (or maybe
> >>>>> [<base>,<index>*<scale>]).
> >>>>
> >>>> Does this comment apply only to AMX instructions?  Are there any
> >>>> issues with disassembler in general?
> >>>
> >>> I'm not aware of any others, perhaps beside some of the more strange
> >>> MPX insns. But with MPX discontinued I don't think there's much point
> >>> worrying about them.
> >>
> >> Lili, please take a look.
> >
> > Hi Jan,
> >
> > Could you help figure out which format I should use? and what's the "n" meaning it the second format, Thanks.
> > [<base>+<index>*<scale>]
> > [<base>+<index>*<scale>n]
> > [<base>,<index>*<scale>]
>
> See my original question: "Is this (not very intuitive) representation
> agreed with Microsoft's MASM team?" I have no contacts there, but I
> would be assuming you (Intel) have.

MASM doesn't always support new ISAs.

> The 'n' was meant to be a literal character 'n', standing for what
> the operation sections of the insns call "start" (while "stride" is
> <index>*<scale>).
>

We don't invent new assembly syntax for AMX.  Disassembler should match
what assembler accepts.

-- 
H.J.