[PATCH] MIPS/gas: Reorganize MIPS specific usage messages
Rongwei Zhang
pudh4418@gmail.com
Tue Jul 21 05:43:22 GMT 2020
Categorize and sort options based on comments from struct md_longopts.
gas/
* config/tc-mips.c (show): Align.
(md_show_usage): Reorganize usage messages
---
gas/config/tc-mips.c | 302 ++++++++++++++++++++++++++-----------------
1 file changed, 186 insertions(+), 116 deletions(-)
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 2d85cb5da1..2ec8c35ce0 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -20311,8 +20311,8 @@ show (FILE *stream, const char *string, int *col_p, int *first_p)
{
if (*first_p)
{
- fprintf (stream, "%24s", "");
- *col_p = 24;
+ fprintf (stream, "%26s", "");
+ *col_p = 26;
}
else
{
@@ -20322,8 +20322,8 @@ show (FILE *stream, const char *string, int *col_p, int *first_p)
if (*col_p + strlen (string) > 72)
{
- fprintf (stream, "\n%24s", "");
- *col_p = 24;
+ fprintf (stream, "\n%26s", "");
+ *col_p = 26;
}
fprintf (stream, "%s", string);
@@ -20338,30 +20338,42 @@ md_show_usage (FILE *stream)
int column, first;
size_t i;
+ fprintf (stream, _("\n\
+MIPS options:\n"));
+ fprintf (stream, _("\n\
+Architectures:\n"));
fprintf (stream, _("\
-MIPS options:\n\
--EB generate big endian output\n\
--EL generate little endian output\n\
--g, -g2 do not remove unneeded NOPs or swap branches\n\
--G NUM allow referencing objects up to NUM bytes\n\
- implicitly with the gp register [default 8]\n"));
+ -mips1 generate MIPS ISA I instructions\n"));
fprintf (stream, _("\
--mips1 generate MIPS ISA I instructions\n\
--mips2 generate MIPS ISA II instructions\n\
--mips3 generate MIPS ISA III instructions\n\
--mips4 generate MIPS ISA IV instructions\n\
--mips5 generate MIPS ISA V instructions\n\
--mips32 generate MIPS32 ISA instructions\n\
--mips32r2 generate MIPS32 release 2 ISA instructions\n\
--mips32r3 generate MIPS32 release 3 ISA instructions\n\
--mips32r5 generate MIPS32 release 5 ISA instructions\n\
--mips32r6 generate MIPS32 release 6 ISA instructions\n\
--mips64 generate MIPS64 ISA instructions\n\
--mips64r2 generate MIPS64 release 2 ISA instructions\n\
--mips64r3 generate MIPS64 release 3 ISA instructions\n\
--mips64r5 generate MIPS64 release 5 ISA instructions\n\
--mips64r6 generate MIPS64 release 6 ISA instructions\n\
--march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
+ -mips2 generate MIPS ISA II instructions\n"));
+ fprintf (stream, _("\
+ -mips3 generate MIPS ISA III instructions\n"));
+ fprintf (stream, _("\
+ -mips4 generate MIPS ISA IV instructions\n"));
+ fprintf (stream, _("\
+ -mips5 generate MIPS ISA V instructions\n"));
+ fprintf (stream, _("\
+ -mips32 generate MIPS32 ISA instructions\n"));
+ fprintf (stream, _("\
+ -mips32r2 generate MIPS32 release 2 ISA instructions\n"));
+ fprintf (stream, _("\
+ -mips32r3 generate MIPS32 release 3 ISA instructions\n"));
+ fprintf (stream, _("\
+ -mips32r5 generate MIPS32 release 5 ISA instructions\n"));
+ fprintf (stream, _("\
+ -mips32r6 generate MIPS32 release 6 ISA instructions\n"));
+ fprintf (stream, _("\
+ -mips64 generate MIPS64 ISA instructions\n"));
+ fprintf (stream, _("\
+ -mips64r2 generate MIPS64 release 2 ISA instructions\n"));
+ fprintf (stream, _("\
+ -mips64r3 generate MIPS64 release 3 ISA instructions\n"));
+ fprintf (stream, _("\
+ -mips64r5 generate MIPS64 release 5 ISA instructions\n"));
+ fprintf (stream, _("\
+ -mips64r6 generate MIPS64 release 6 ISA instructions\n"));
+ fprintf (stream, _("\
+ -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
first = 1;
@@ -20371,9 +20383,11 @@ MIPS options:\n\
fputc ('\n', stream);
fprintf (stream, _("\
--mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
--no-mCPU don't generate code specific to CPU.\n\
- For -mCPU and -no-mCPU, CPU must be one of:\n"));
+ -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n"));
+ fprintf (stream, _("\
+ -no-mCPU don't generate code specific to CPU\n"));
+ fprintf (stream, _("\
+ For -mCPU and -no-mCPU, CPU must be one of:\n"));
first = 1;
@@ -20383,118 +20397,100 @@ MIPS options:\n\
show (stream, "4650", &column, &first);
fputc ('\n', stream);
+ fprintf (stream, _("\n\
+Application Specific Extensions (ASEs):\n"));
fprintf (stream, _("\
--mips16 generate mips16 instructions\n\
--no-mips16 do not generate mips16 instructions\n"));
+ -mcrc generate CRC instructions\n\
+ -mno-crc do not generate CRC instructions\n"));
fprintf (stream, _("\
--mmips16e2 generate MIPS16e2 instructions\n\
--mno-mips16e2 do not generate MIPS16e2 instructions\n"));
+ -mdsp generate DSP instructions\n\
+ -mno-dsp do not generate DSP instructions\n"));
fprintf (stream, _("\
--mmicromips generate microMIPS instructions\n\
--mno-micromips do not generate microMIPS instructions\n"));
+ -mdspr2 generate DSP R2 instructions\n\
+ -mno-dspr2 do not generate DSP R2 instructions\n"));
fprintf (stream, _("\
--msmartmips generate smartmips instructions\n\
--mno-smartmips do not generate smartmips instructions\n"));
+ -mdspr3 generate DSP R3 instructions\n\
+ -mno-dspr3 do not generate DSP R3 instructions\n"));
fprintf (stream, _("\
--mdsp generate DSP instructions\n\
--mno-dsp do not generate DSP instructions\n"));
+ -mginv generate Global INValidate (GINV) instructions\n\
+ -mno-ginv do not generate Global INValidate instructions\n"));
fprintf (stream, _("\
--mdspr2 generate DSP R2 instructions\n\
--mno-dspr2 do not generate DSP R2 instructions\n"));
+ -mloongson-cam generate Loongson Content Address Memory (CAM)\n\
+ instructions\n\
+ -mno-loongson-cam do not generate Loongson CAM instructions\n"));
fprintf (stream, _("\
--mdspr3 generate DSP R3 instructions\n\
--mno-dspr3 do not generate DSP R3 instructions\n"));
+ -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
+ -mno-loongson-ext do not generate Loongson EXTensions instructions\n"));
fprintf (stream, _("\
--mmt generate MT instructions\n\
--mno-mt do not generate MT instructions\n"));
+ -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
+ -mno-loongson-ext2 do not generate Loongson EXTensions R2 instructions\n"));
fprintf (stream, _("\
--mmcu generate MCU instructions\n\
--mno-mcu do not generate MCU instructions\n"));
+ -mloongson-mmi generate Loongson MultiMedia extensions Instructions\n\
+ (MMI) instructions\n\
+ -mno-loongson-mmi do not generate Loongson MMI instructions\n"));
fprintf (stream, _("\
--mmsa generate MSA instructions\n\
--mno-msa do not generate MSA instructions\n"));
+ -mmcu generate MCU instructions\n\
+ -mno-mcu do not generate MCU instructions\n"));
fprintf (stream, _("\
--mxpa generate eXtended Physical Address (XPA) instructions\n\
--mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
+ -mmicromips generate microMIPS instructions\n\
+ -mno-micromips do not generate microMIPS instructions\n"));
fprintf (stream, _("\
--mvirt generate Virtualization instructions\n\
--mno-virt do not generate Virtualization instructions\n"));
+ -mips16 generate mips16 instructions\n\
+ -no-mips16 do not generate mips16 instructions\n"));
fprintf (stream, _("\
--mcrc generate CRC instructions\n\
--mno-crc do not generate CRC instructions\n"));
+ -mmips16e2 generate MIPS16e2 instructions\n\
+ -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
fprintf (stream, _("\
--mginv generate Global INValidate (GINV) instructions\n\
--mno-ginv do not generate Global INValidate instructions\n"));
+ -mmsa generate MSA instructions\n\
+ -mno-msa do not generate MSA instructions\n"));
fprintf (stream, _("\
--mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
--mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
+ -mmt generate MT instructions\n\
+ -mno-mt do not generate MT instructions\n"));
fprintf (stream, _("\
--mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
--mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
+ -msmartmips generate smartmips instructions\n\
+ -mno-smartmips do not generate smartmips instructions\n"));
fprintf (stream, _("\
--mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
--mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
+ -mvirt generate Virtualization instructions\n\
+ -mno-virt do not generate Virtualization instructions\n"));
+ fprintf (stream, _("\
+ -mxpa generate eXtended Physical Address (XPA)\n\
+ instructions\n\
+ -mno-xpa do not generate XPA instructions\n"));
+
+ fprintf (stream, _("\n\
+Bug fixes:\n"));
fprintf (stream, _("\
--mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
--mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
+ -mfix-24k insert a nop after ERET and DERET instructions\n"));
fprintf (stream, _("\
--minsn32 only generate 32-bit microMIPS instructions\n\
--mno-insn32 generate all microMIPS instructions\n"));
+ -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n"));
+ fprintf (stream, _("\
+ -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n"));
+ fprintf (stream, _("\
+ -mfix-loongson2f-nop work around Loongson2F NOP instructions\n"));
#if DEFAULT_MIPS_FIX_LOONGSON3_LLSC
fprintf (stream, _("\
--mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\
--mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n"));
+ -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\
+ -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n"));
#else
fprintf (stream, _("\
--mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
--mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n"));
+ -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
+ -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n"));
#endif
fprintf (stream, _("\
--mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
--mfix-loongson2f-nop work around Loongson2F NOP errata\n\
--mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
--mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\
--mfix-vr4120 work around certain VR4120 errata\n\
--mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
--mfix-24k insert a nop after ERET and DERET instructions\n\
--mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
--mfix-r5900 work around R5900 short loop errata\n\
--mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
--mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
--msym32 assume all symbols have 32-bit values\n\
--O0 do not remove unneeded NOPs, do not swap branches\n\
--O, -O1 remove unneeded NOPs, do not swap branches\n\
--O2 remove unneeded NOPs and swap branches\n\
---trap, --no-break trap exception on div by 0 and mult overflow\n\
---break, --no-trap break exception on div by 0 and mult overflow\n"));
+ -mfix-r5900 work around R5900 short loop errata\n"));
fprintf (stream, _("\
--mhard-float allow floating-point instructions\n\
--msoft-float do not allow floating-point instructions\n\
--msingle-float only allow 32-bit floating-point operations\n\
--mdouble-float allow 32-bit and 64-bit floating-point operations\n\
---[no-]construct-floats [dis]allow floating point values to be constructed\n\
---[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
--mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
--mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
--mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
-
- first = 1;
-
- show (stream, "legacy", &column, &first);
- show (stream, "2008", &column, &first);
-
- fputc ('\n', stream);
+ -mfix-vr4120 work around certain VR4120 errata\n"));
+ fprintf (stream, _("\
+ -mfix-vr4130 work around VR4130 mflo/mfhi errata\n"));
+ fprintf (stream, _("\n\
+ELF-specific options:\n"));
+ fprintf (stream, _("\
+ -call_nonpic generate non-PIC code that can operate with DSOs\n"));
fprintf (stream, _("\
--KPIC, -call_shared generate SVR4 position independent code\n\
--call_nonpic generate non-PIC code that can operate with DSOs\n\
--mvxworks-pic generate VxWorks position independent code\n\
--non_shared do not generate code that can operate with DSOs\n\
--xgot assume a 32 bit GOT\n\
--mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
--mshared, -mno-shared disable/enable .cpload optimization for\n\
- position dependent (non shared) code\n\
--mabi=ABI create ABI conformant object file for:\n"));
+ -call_shared, -KPIC generate SVR4 position independent code\n"));
+ fprintf (stream, _("\
+ -mabi=ABI create ABI conformant object file for:\n"));
first = 1;
@@ -20507,14 +20503,88 @@ MIPS options:\n\
fputc ('\n', stream);
fprintf (stream, _("\
--32 create o32 ABI object file%s\n"),
+ -32 create o32 ABI object file%s\n"),
MIPS_DEFAULT_ABI == O32_ABI ? _(" (default)") : "");
fprintf (stream, _("\
--n32 create n32 ABI object file%s\n"),
+ -n32 create n32 ABI object file%s\n"),
MIPS_DEFAULT_ABI == N32_ABI ? _(" (default)") : "");
fprintf (stream, _("\
--64 create 64 ABI object file%s\n"),
+ -64 create 64 ABI object file%s\n"),
MIPS_DEFAULT_ABI == N64_ABI ? _(" (default)") : "");
+ fprintf (stream, _("\
+ -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
+
+ first = 1;
+
+ show (stream, "legacy", &column, &first);
+ show (stream, "2008", &column, &first);
+
+ fputc ('\n', stream);
+
+ fprintf (stream, _("\
+ -mpdr, -mno-pdr enable/disable creation of .pdr section\n"));
+ fprintf (stream, _("\
+ -mvxworks-pic generate VxWorks position independent code\n"));
+ fprintf (stream, _("\
+ -non_shared do not generate code that can operate with DSOs\n"));
+ fprintf (stream, _("\
+ -xgot assume a 32 bit GOT\n"));
+
+ fprintf (stream, _("\n\
+Miscellaneous options:\n"));
+
+ fprintf (stream, _("\
+ --break, --no-trap break exception on div by 0 and mult overflow\n"));
+ fprintf (stream, _("\
+ --construct-floats allow floating point values to be constructed\n"));
+ fprintf (stream, _("\
+ --no-construct-floats disallow floating point values to be constructed\n"));
+ fprintf (stream, _("\
+ -EB generate big endian output\n"));
+ fprintf (stream, _("\
+ -EL generate little endian output\n"));
+ fprintf (stream, _("\
+ -g, -g2 do not remove unneeded NOPs or swap branches\n"));
+ fprintf (stream, _("\
+ -G NUM allow referencing objects up to NUM bytes\n\
+ implicitly with the gp register [default 8]\n"));
+ fprintf (stream, _("\
+ -mdouble-float allow 32-bit and 64-bit floating-point operations\n"));
+ fprintf (stream, _("\
+ -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n"));
+ fprintf (stream, _("\
+ -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n"));
+ fprintf (stream, _("\
+ -mhard-float allow floating-point instructions\n"));
+ fprintf (stream, _("\
+ -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n"));
+ fprintf (stream, _("\
+ -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n"));
+ fprintf (stream, _("\
+ -minsn32 only generate 32-bit microMIPS instructions\n"));
+ fprintf (stream, _("\
+ -mno-insn32 generate all microMIPS instructions\n"));
+ fprintf (stream, _("\
+ -mshared, -mno-shared disable/enable .cpload optimization for\n\
+ position dependent (non shared) code\n"));
+ fprintf (stream, _("\
+ -msingle-float only allow 32-bit floating-point operations\n"));
+ fprintf (stream, _("\
+ -msoft-float do not allow floating-point instructions\n"));
+ fprintf (stream, _("\
+ -msym32 assume all symbols have 32-bit values\n"));
+ fprintf (stream, _("\
+ -O0 do not remove unneeded NOPs, do not swap branches\n"));
+ fprintf (stream, _("\
+ -O, -O1 remove unneeded NOPs, do not swap branches\n"));
+ fprintf (stream, _("\
+ -O2 remove unneeded NOPs and swap branches\n"));
+ fprintf (stream, _("\
+ --relax-branch allow out-of-range branches to be relaxed\n"));
+ fprintf (stream, _("\
+ --no-relax-branch disallow out-of-range branches to be relaxed\n"));
+ fprintf (stream, _("\
+ --trap, --no-break trap exception on div by 0 and mult overflow\n"));
}
#ifdef TE_IRIX
--
2.26.2
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