[PATCH 00/19] x86: further disassembler fixes and folding

[H.J. Lu]

On Mon, Jul 13, 2020 at 2:31 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> While the diffstat for this series (see below) is imo quite nice,
> this still is only a further step towards the goal of making the
> code overall more manageable by reducing the number of table
> entries/branches, enumerators, macros, helper functions, and case
> labels/blocks, many of which are currently redundant with one
> another. Bugs are again getting fixed and other improvements made
> along the road, as things were recognized.
>
> 01: x86-64: fold ILP32 test expectations
> 02: x86: drop dead code from OP_IMREG()
> 03: x86-64: don't hide an empty but meaningless REX prefix
> 04: x86: avoid attaching suffix to register-only CRC32
> 05: x86: don't disassemble MOVBE with two suffixes
> 06: x86: fold VCMP_Fixup() into CMP_Fixup()
> 07: x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel mode
> 08: x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W}
> 09: x86: merge/move logic determining the EVEX disp8 shift
> 10: x86: replace %LW by %DQ
> 11: x86: drop Vex128 and Vex256
> 12: x86: drop need_vex_reg
> 13: x86: drop further EVEX table entries that can be served by VEX ones
> 14: x86: simplify decode of opcodes valid with (embedded) 66 prefix only
> 15: x86: also use %BW / %DQ for kshift*
> 16: x86: simplify decode of opcodes valid only without any (embedded) prefix
> 17: x86: drop Rdq, Rd, and MaskR
> 18: x86: drop Rm and the 'L' macro
> 19: x86/Intel: debug registers are named DRn
>

OK for all.

Thanks.

-- 
H.J.