[PATCH v5 5/5] x86-64: Intel64 adjustments for insns dealing with far pointers

[Jan Beulich]

On 11.02.2020 12:52, H.J. Lu wrote:
> On Tue, Feb 11, 2020 at 2:26 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> AMD and Intel differ in their handling of far indirect branches as well
>> as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
>> how the latter three were hybrids so far, while far branches were fully
>> AMD-like.)
>>
>> gas/
>> 2020-02-XX  Jan Beulich  <jbeulich@suse.com>
>>
>>         PR gas/24546
>>         * config/tc-i386-intel.c (i386_intel_operand): Also handle CALL/JMP
>>         in O_tbyte_ptr case.
>>         * doc/c-i386.texi: Mention far call and full pointer load ISA
>>         differences.
>>         * testsuite/gas/i386/x86-64-branch-3.s,
>>         testsuite/gas/i386/x86-64-intel64.s: Add 64-bit far call cases.
>>         * testsuite/gas/i386/x86-64-branch-3.d,
>>         testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
>>         * testsuite/gas/i386/x86-64-branch-5.l,
>>         testsuite/gas/i386/x86-64-branch-5.s: New.
>>         * testsuite/gas/i386/i386.exp: Run new test.
>>
>> opcodes/
>> 2020-02-XX  Jan Beulich  <jbeulich@suse.com>
>>
>>         PR gas/24546
>>         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
>>         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
>>         Amd64 and Intel64 templates.
>>         (call, jmp): Likewise for far indirect variants. Dro
>>         Unspecified.
>>         * i386-tbl.h: Re-generate.
> 
> OK.

There'll need to be a v6, as I've spotted an issue with non-64-bit
code in -mintel64 mode (which occurred to me only when starting to
deal with the vendor difference also for Jcc). v4 had an adjustment
for this, and I wrongly thought it could be dropped altogether when
re-basing over your Intel64-only change. (On the positive side I
think a few other templates will be able to be folded as a follow-on
to the fix I'm intending to make.)

Jan