[PATCH] x86-64: Properly encode and decode movsxd

[Jan Beulich]

On 23.01.2020 21:24, H.J. Lu wrote:
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-movsxd-intel.d
> @@ -0,0 +1,26 @@
> +#source: x86-64-movsxd.s
> +#as:
> +#objdump: -dw -Mintel
> +#name: x86-64 movsxd (AMD64) (Intel mode)
> +
> +.*: +file format .*
> +
> +Disassembly of section .text:
> +
> +0+ <_start>:
> + +[a-f0-9]+:	48 63 c8             	movsxd rcx,eax
> + +[a-f0-9]+:	48 63 08             	movsxd rcx,DWORD PTR \[rax\]
> + +[a-f0-9]+:	63 c8                	movsxd ecx,eax
> + +[a-f0-9]+:	63 08                	movsxd ecx,DWORD PTR \[rax\]
> + +[a-f0-9]+:	66 63 c8             	movsxd cx,eax
> + +[a-f0-9]+:	66 63 08             	movsxd cx,DWORD PTR \[rax\]
> + +[a-f0-9]+:	48 63 c8             	movsxd rcx,eax
> + +[a-f0-9]+:	48 63 08             	movsxd rcx,DWORD PTR \[rax\]
> + +[a-f0-9]+:	48 63 08             	movsxd rcx,DWORD PTR \[rax\]
> + +[a-f0-9]+:	63 c8                	movsxd ecx,eax
> + +[a-f0-9]+:	63 08                	movsxd ecx,DWORD PTR \[rax\]
> + +[a-f0-9]+:	63 08                	movsxd ecx,DWORD PTR \[rax\]
> + +[a-f0-9]+:	66 63 c8             	movsxd cx,eax
> + +[a-f0-9]+:	63 08                	movsxd ecx,DWORD PTR \[rax\]

FTR this line as well as ...

> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-movsxd.d
> @@ -0,0 +1,25 @@
> +#as:
> +#objdump: -dw
> +#name: x86-64 movsxd (AMD64)
> +
> +.*: +file format .*
> +
> +Disassembly of section .text:
> +
> +0+ <_start>:
> + +[a-f0-9]+:	48 63 c8             	movslq %eax,%rcx
> + +[a-f0-9]+:	48 63 08             	movslq \(%rax\),%rcx
> + +[a-f0-9]+:	63 c8                	movsxd %eax,%ecx
> + +[a-f0-9]+:	63 08                	movsxd \(%rax\),%ecx
> + +[a-f0-9]+:	66 63 c8             	movsxd %eax,%cx
> + +[a-f0-9]+:	66 63 08             	movsxd \(%rax\),%cx
> + +[a-f0-9]+:	48 63 c8             	movslq %eax,%rcx
> + +[a-f0-9]+:	48 63 08             	movslq \(%rax\),%rcx
> + +[a-f0-9]+:	48 63 08             	movslq \(%rax\),%rcx
> + +[a-f0-9]+:	63 c8                	movsxd %eax,%ecx
> + +[a-f0-9]+:	63 08                	movsxd \(%rax\),%ecx
> + +[a-f0-9]+:	63 08                	movsxd \(%rax\),%ecx
> + +[a-f0-9]+:	66 63 c8             	movsxd %eax,%cx
> + +[a-f0-9]+:	63 08                	movsxd \(%rax\),%ecx

... as this one contradict ...

> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-movsxd.s
> @@ -0,0 +1,20 @@
> +# 64-bit only MOVSXD with AMD64 ISA
> +	.text
> +_start:
> +	movslq	%eax, %rcx
> +	movslq	(%rax), %rcx
> +	movsxd	%eax, %ecx
> +	movsxd	(%rax), %ecx
> +	movsxd	%eax, %cx
> +	movsxd	(%rax), %cx
> +
> +	.intel_syntax noprefix
> +	movsxd	rcx, eax
> +	movsxd	rcx, DWORD PTR [rax]
> +	movsxd	rcx, [rax]
> +	movsxd	ecx, eax
> +	movsxd	ecx, DWORD PTR [rax]
> +	movsxd	ecx, [rax]
> +	movsxd	cx, eax
> +	movsxd	cx, DWORD PTR [rax]

... this respective source line. I found this while re-basing my
previously submitted patch, which - as said before - deals with
the whole set of issues in a more generic way, and which caused
this wrong test to fail. No need to create/submit a fix - the
re-worked patch is doing fine, but before submitting I first
want to address the other inconsistencies that you've
introduced by be4c5e58bd ("x86: Always disallow double word
suffix with word general register") changing check_long_reg()
without also changing check_{byte,word}_reg(), as previously
pointed out.

This looks to be yet another instance of a testcase having got
created by taking what the assembler happens to produce,
instead of putting in expectations of what the assembler
_should_ produce if it worked correctly.

Jan