[PATCH v2 4/6] RISC-V: Recognize riscvNNbe* as target

[Nelson Chu]

On Sun, Dec 20, 2020 at 7:29 PM Marcus Comstedt <marcus@mc.pp.se> wrote:
>
> bfd/
>         * config.bfd (riscvbe-*-*, riscv32be*-*-*),
>         (riscv64be*-*-*): Add target.
>
> ld/
>         * configure.tgt: Add riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*,
>         riscv32be*-*-linux*, and riscv64be*-*-linux*.
> ---
>  bfd/config.bfd   | 10 ++++++++++
>  config.sub       |  2 +-
>  ld/configure.tgt | 25 +++++++++++++++++++++----
>  3 files changed, 32 insertions(+), 5 deletions(-)
>
> diff --git a/bfd/config.bfd b/bfd/config.bfd
> index 2ae8b1a4cc..f792bd01df 100644
> --- a/bfd/config.bfd
> +++ b/bfd/config.bfd
> @@ -1158,11 +1158,21 @@ case "${targ}" in
>      ;;
>
>  #ifdef BFD64
> +  riscvbe-*-* | riscv32be*-*-*)
> +    targ_defvec=riscv_elf32_be_vec
> +    targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
> +    want64=true
> +    ;;
>    riscv-*-* | riscv32*-*-*)
>      targ_defvec=riscv_elf32_vec
>      targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
>      want64=true
>      ;;
> +  riscv64be*-*-*)
> +    targ_defvec=riscv_elf64_be_vec
> +    targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
> +    want64=true
> +    ;;
>    riscv64*-*-*)
>      targ_defvec=riscv_elf64_vec
>      targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"

I'm OK with this.  But we don't own the ISA spec, so we need to
discuss the new target triplets with RISC-V International in the
psabi, here is the open issue I opened,
https://github.com/riscv/riscv-elf-psabi-doc/issues/167.

> diff --git a/ld/configure.tgt b/ld/configure.tgt
> index 70359301b5..1a5cd476c4 100644
> --- a/ld/configure.tgt
> +++ b/ld/configure.tgt
> @@ -738,21 +738,38 @@ powerpc-*-windiss*)       targ_emul=elf32ppcwindiss
>                         ;;
>  pru*-*-*)              targ_emul=pruelf
>                         ;;
> +riscv32be*-*-linux*)   targ_emul=elf32briscv
> +                       targ_extra_emuls="elf32briscv_ilp32f elf32briscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64"
> +                       targ_extra_libpath=$targ_extra_emuls
> +                       ;;
>  riscv32*-*-linux*)     targ_emul=elf32lriscv
> -                       targ_extra_emuls="elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64"
> +                       targ_extra_emuls="elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64"
> +                       targ_extra_libpath=$targ_extra_emuls
> +                       ;;
> +riscvbe-*-* | riscv32be*-*-*)
> +                       targ_emul=elf32briscv
> +                       targ_extra_emuls="elf64briscv elf32lriscv elf64lriscv"
>                         targ_extra_libpath=$targ_extra_emuls
>                         ;;
>  riscv-*-* | riscv32*-*-*)
>                         targ_emul=elf32lriscv
> -                       targ_extra_emuls="elf64lriscv"
> +                       targ_extra_emuls="elf64lriscv elf32briscv elf64briscv"
> +                       targ_extra_libpath=$targ_extra_emuls
> +                       ;;
> +riscv64be*-*-linux*)   targ_emul=elf64briscv
> +                       targ_extra_emuls="elf64briscv_lp64f elf64briscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32"
>                         targ_extra_libpath=$targ_extra_emuls
>                         ;;
>  riscv64*-*-linux*)     targ_emul=elf64lriscv
> -                       targ_extra_emuls="elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32"
> +                       targ_extra_emuls="elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32"
> +                       targ_extra_libpath=$targ_extra_emuls
> +                       ;;
> +riscv64be*-*-*)                targ_emul=elf64briscv
> +                       targ_extra_emuls="elf32briscv elf64lriscv elf32lriscv"
>                         targ_extra_libpath=$targ_extra_emuls
>                         ;;
>  riscv64*-*-*)          targ_emul=elf64lriscv
> -                       targ_extra_emuls="elf32lriscv"
> +                       targ_extra_emuls="elf32lriscv elf64briscv elf32briscv"
>                         targ_extra_libpath=$targ_extra_emuls
>                         ;;

I get at least 11 riscv ld testcases failed,

FAIL: call relaxation with alignment
FAIL: lui to c.lui relaxation
FAIL: c.lui to c.li relaxation
FAIL: jalr zero-offset symbols
FAIL: ld-riscv-elf/attr-merge-arch-01
FAIL: ld-riscv-elf/attr-merge-arch-02
FAIL: ld-riscv-elf/attr-merge-arch-03
FAIL: ld-riscv-elf/attr-merge-arch-failed-01
FAIL: ld-riscv-elf/attr-merge-arch-failed-02
FAIL: Weak reference 32
FAIL: Weak reference 64

The root cause is that these testcases set "-melf[32|64]lriscv" to
choose the right emulate files.  It's fine in the past since we
haven't support big endians, but we should find a way to fix them
after applying the big endian patches.  Ideally, I think we can refer
to what MIPS did in their ld-mips-elf/mips-elf.exp, use the
abi_asflags/abi_ldflags to choose the abi and emulate files.  But in
the short-term, I can accept the workaround that set your new
assembler option, -mlittle-endian, to always test the little endian
and pass these test cases temporarily.

Thanks
Nelson