[PATCH 9/9] RISC-V: Mention -mbig-endian and -mlittle-endian in doc

[Marcus Comstedt]

---
 gas/doc/as.texi      |  1 +
 gas/doc/c-riscv.texi | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 983cec3cbf..2f8142472f 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -536,6 +536,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
    [@b{-march}=@var{ISA}]
    [@b{-mabi}=@var{ABI}]
+   [@b{-mlittle}|@b{-mlittle-endian}|@b{-mbig}|@b{-mbig-endian}]
 @end ifset
 @ifset RL78
 
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index d63b1f3990..481bfbbfbb 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -99,6 +99,16 @@ read-only CSR can not be written by the CSR instructions.
 @cindex @samp{-mno-csr-check} option, RISC-V
 @item -mno-csr-check
 Don't do CSR checking.
+
+@cindex @samp{-mlittle} option, RISC-V
+@cindex @samp{-mlittle-endian} option, RISC-V
+@item -mlittle, -mlittle-endian
+Generate code for a little endian machine.
+
+@cindex @samp{-mbig} option, RISC-V
+@cindex @samp{-mbig-endian} option, RISC-V
+@item -mbig, -mbig-endian
+Generate code for a big endian machine.
 @end table
 @c man end
 
-- 
2.26.2