[PATCH 6/9] RISC-V: Change big endian triplets from riscvNN*_be to riscvNNbe*

[Marcus Comstedt]

---
 bfd/config.bfd   | 4 ++--
 config.sub       | 2 +-
 ld/configure.tgt | 8 ++++----
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/bfd/config.bfd b/bfd/config.bfd
index 2b37358f58..f792bd01df 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -1158,7 +1158,7 @@ case "${targ}" in
     ;;
 
 #ifdef BFD64
-  riscv_be-*-* | riscv32*_be-*-*)
+  riscvbe-*-* | riscv32be*-*-*)
     targ_defvec=riscv_elf32_be_vec
     targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
     want64=true
@@ -1168,7 +1168,7 @@ case "${targ}" in
     targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
     want64=true
     ;;
-  riscv64*_be-*-*)
+  riscv64be*-*-*)
     targ_defvec=riscv_elf64_be_vec
     targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
     want64=true
diff --git a/config.sub b/config.sub
index 9dc3eb9e51..7bb0fa6b83 100755
--- a/config.sub
+++ b/config.sub
@@ -1227,7 +1227,7 @@ case $cpu-$vendor in
 			| powerpc | powerpc64 | powerpc64le | powerpcle | powerpcspe \
 			| pru \
 			| pyramid \
-			| riscv | riscv32 | riscv64 | riscv_be | riscv32_be | riscv64_be \
+			| riscv | riscv32 | riscv64 | riscvbe | riscv32be | riscv64be \
 			| rl78 | romp | rs6000 | rx \
 			| score \
 			| sh | shl \
diff --git a/ld/configure.tgt b/ld/configure.tgt
index b167c5db06..1a5cd476c4 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -738,7 +738,7 @@ powerpc-*-windiss*)	targ_emul=elf32ppcwindiss
 			;;
 pru*-*-*)		targ_emul=pruelf
 			;;
-riscv32*_be-*-linux*)	targ_emul=elf32briscv
+riscv32be*-*-linux*)	targ_emul=elf32briscv
 			targ_extra_emuls="elf32briscv_ilp32f elf32briscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
@@ -746,7 +746,7 @@ riscv32*-*-linux*)	targ_emul=elf32lriscv
 			targ_extra_emuls="elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
-riscv_be-*-* | riscv32*_be-*-*)
+riscvbe-*-* | riscv32be*-*-*)
 			targ_emul=elf32briscv
 			targ_extra_emuls="elf64briscv elf32lriscv elf64lriscv"
 			targ_extra_libpath=$targ_extra_emuls
@@ -756,7 +756,7 @@ riscv-*-* | riscv32*-*-*)
 			targ_extra_emuls="elf64lriscv elf32briscv elf64briscv"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
-riscv64*_be-*-linux*)	targ_emul=elf64briscv
+riscv64be*-*-linux*)	targ_emul=elf64briscv
 			targ_extra_emuls="elf64briscv_lp64f elf64briscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
@@ -764,7 +764,7 @@ riscv64*-*-linux*)	targ_emul=elf64lriscv
 			targ_extra_emuls="elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
-riscv64*_be-*-*)	targ_emul=elf64briscv
+riscv64be*-*-*)		targ_emul=elf64briscv
 			targ_extra_emuls="elf32briscv elf64lriscv elf32lriscv"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
-- 
2.26.2