[PATCH 0/9] RISC-V: Implement support for big endian targets
Marcus Comstedt
marcus@mc.pp.se
Sat Dec 19 13:17:19 GMT 2020
The following patch set implements support for big endian targets
(both 32 and 64 bit) in binutils. It was originally submitted as
https://github.com/riscv/riscv-binutils-gdb/pull/237
but the maintainers of the riscv-binutils-gdb repository asked me to
submit it here instead.
Big endian RISC-V is specified by The RISC-V Instruction Set Manual
Volume I: Unprivileged ISA, Version 20191213, as available on riscv.org.
Implementations exist in the form of FPGA gateware (VexRiscv, which
can be configured in big endian mode) and the RISC-V ISA simulator
"spike".
Of importance here is the choice of triplet identifier, as this would
be difficult (or at least awkward) to change later. I originally
opted for riscv{32,64}*_be, but changed it to riscv{32,64}be* at the
request of Kito Cheng. I think this looks nicer, although it could
potentially cause confusion with the "RV32EB" and "RV64EB" ISA:s,
which denote the embedded base integer instruction set with bit
manipulation extensions (regardless of endianness).
Copyright assignment of these patches have been filed with the FSF
as RT:1657178.
I also have patches for gcc and gnu config, but I assume binutils is
the right place to start for adding support?
Thanks in advance to any and all reviewers.
// Marcus
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