[PATCH 1/3] RISC-V: Support riscv bitmanip instructions.
Nelson Chu
nelson.chu@sifive.com
Tue Dec 15 15:11:03 GMT 2020
From: Claire Xenia Wolf <claire@symbioticeda.com>
This patch is basically based on the github branch riscv-binutils-2.35-rvb,
which is in the riscv/riscv-binutils-gdb repo,
https://github.com/riscv/riscv-binutils-gdb/tree/riscv-binutils-2.35-rvb
2020-12-15 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Maxim Blinov <maxim.blinov@embecosm.com>
Kito Cheng <kito.cheng@sifive.com>
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Add b and zb* extensions.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_B*.
(riscv_get_default_ext_version): Do not check the default_isa_spec for
draft extensions.
(perm): New function. Used to handle the bitmanip pseudos.
(macro, macro_build): Handle bitmanip pseudos..
(validate_riscv_insn): Add support for bitmanip instructions.
(riscv_ip): Add new operand '|'.
* testsuite/gas/riscv/attribute-draft-b.d: New testcases.
* testsuite/gas/riscv/bitmanip-insns-32.d: Likewise.
* testsuite/gas/riscv/bitmanip-insns-64.d: Likewise.
* testsuite/gas/riscv/bitmanip-insns-pseudo-32.d: Likewise.
* testsuite/gas/riscv/bitmanip-insns-pseudo-64.d: Likewise.
* testsuite/gas/riscv/bitmanip-insns-pseudo.s: Likewise.
* testsuite/gas/riscv/bitmanip-insns.s: Likewise.
include/
* opcode/riscv-opc.h: Add bitmanip MASK/MATCH/DECLARE_INSN.
* opcode/riscv.h: Add M_PERM to enum macro.
(riscv_insn_class): Add INSN_CLASS_B*.
(riscv_isa_spec_class): Add ISA_SPEC_CLASS_DRAFT.
opcodes/
* riscv-dis.c (print_insn_args): Handle opernads '|' and 'r'.
* riscv-opc.c (riscv_opcodes): Add bitmanip instructions.
---
bfd/elfxx-riscv.c | 4 +-
gas/config/tc-riscv.c | 119 ++++++++-
gas/testsuite/gas/riscv/attribute-draft-b.d | 6 +
gas/testsuite/gas/riscv/bitmanip-insns-32.d | 97 +++++++
gas/testsuite/gas/riscv/bitmanip-insns-64.d | 177 +++++++++++++
gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d | 61 +++++
gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d | 84 ++++++
gas/testsuite/gas/riscv/bitmanip-insns-pseudo.s | 85 ++++++
gas/testsuite/gas/riscv/bitmanip-insns.s | 204 +++++++++++++++
include/opcode/riscv-opc.h | 287 +++++++++++++++++++++
include/opcode/riscv.h | 17 +-
opcodes/riscv-dis.c | 7 +
opcodes/riscv-opc.c | 224 +++++++++++++++-
13 files changed, 1365 insertions(+), 7 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/attribute-draft-b.d
create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-32.d
create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-64.d
create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-pseudo.s
create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 35e46fa..016905d 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1597,7 +1597,9 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
static const char * const riscv_std_z_ext_strtab[] =
{
- "zicsr", "zifencei", NULL
+ "zicsr", "zifencei",
+ "zba", "zbb", "zbc", "zbe", "zbf", "zbm", "zbp", "zbr", "zbs", "zbt",
+ NULL
};
static const char * const riscv_std_s_ext_strtab[] =
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index ca7e52a..ae3a8ad 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -251,6 +251,43 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
case INSN_CLASS_ZIFENCEI:
return riscv_subset_supports ("zifencei");
+ case INSN_CLASS_B_OR_ZBA:
+ return (riscv_subset_supports ("b")
+ || riscv_subset_supports ("zba"));
+ case INSN_CLASS_B_OR_ZBB:
+ return (riscv_subset_supports ("b")
+ || riscv_subset_supports ("zbb"));
+ case INSN_CLASS_B_OR_ZBC:
+ return (riscv_subset_supports ("b")
+ || riscv_subset_supports ("zbc"));
+ case INSN_CLASS_B_OR_ZBE:
+ return (riscv_subset_supports ("b")
+ || riscv_subset_supports ("zbe"));
+ case INSN_CLASS_B_OR_ZBF:
+ return (riscv_subset_supports ("b")
+ || riscv_subset_supports ("zbf"));
+ case INSN_CLASS_B_OR_ZBM:
+ return (riscv_subset_supports ("b")
+ || riscv_subset_supports ("zbm"));
+ case INSN_CLASS_B_OR_ZBP:
+ return (riscv_subset_supports ("b")
+ || riscv_subset_supports ("zbp"));
+ case INSN_CLASS_ZBR:
+ return riscv_subset_supports ("zbr");
+ case INSN_CLASS_B_OR_ZBS:
+ return (riscv_subset_supports ("b")
+ || riscv_subset_supports ("zbs"));
+ case INSN_CLASS_ZBT:
+ return riscv_subset_supports ("zbt");
+ case INSN_CLASS_B_OR_ZBB_OR_ZBP:
+ return (riscv_subset_supports ("b")
+ || riscv_subset_supports ("zbb")
+ || riscv_subset_supports ("zbp"));
+ case INSN_CLASS_B_OR_ZBF_OR_ZBP:
+ return (riscv_subset_supports ("b")
+ || riscv_subset_supports ("zbf")
+ || riscv_subset_supports ("zbp"));
+
default:
as_fatal ("Unreachable");
return FALSE;
@@ -296,7 +333,8 @@ riscv_get_default_ext_version (const char *name,
&& ext->name
&& strcmp (ext->name, name) == 0)
{
- if (ext->isa_spec_class == default_isa_spec)
+ if (ext->isa_spec_class == ISA_SPEC_CLASS_DRAFT
+ || ext->isa_spec_class == default_isa_spec)
{
*major_version = ext->major_version;
*minor_version = ext->minor_version;
@@ -970,6 +1008,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case '(': break;
case ')': break;
case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
+ case '|': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
case 'A': break;
case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
@@ -1249,6 +1288,15 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
INSERT_OPERAND (RS2, insn, va_arg (args, int));
continue;
+ case 'r':
+ INSERT_OPERAND (RS3, insn, va_arg (args, int));
+ continue;
+
+ case '<':
+ case '|':
+ INSERT_OPERAND (SHAMTW, insn, va_arg (args, int));
+ continue;
+
case '>':
INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
continue;
@@ -1450,6 +1498,58 @@ riscv_ext (int destreg, int srcreg, unsigned shift, bfd_boolean sign)
}
}
+static void
+perm (int rd, int rs1, const char *op)
+{
+ const char *insn = NULL;
+ const char *p = op;
+ int shamt = 0;
+ int shfl = 0;
+
+ switch (p[0])
+ {
+ case 'r': insn = "grevi"; shamt = xlen-1; p += 3; break;
+ case 'o': insn = "gorci"; shamt = xlen-1; p += 3; break;
+ case 'z': insn = "shfli"; shamt = xlen/2-1; p += 3; shfl = 1; break;
+ case 'u': insn = "unshfli"; shamt = xlen/2-1; p += 5; shfl = 1; break;
+ default: as_fatal (_("internal error: bad permutation pseudo-instruction %s"), op);
+ }
+
+ switch (p[0])
+ {
+ case '2': shamt &= shamt << 1; p += 1; break;
+ case '4': shamt &= shamt << 2; p += 1; break;
+ case '8': shamt &= shamt << 3; p += 1; break;
+ case '1': shamt &= shamt << 4; p += 2; break;
+ case '3': shamt &= shamt << 5; p += 2;
+ }
+
+ if (p[0])
+ {
+ if (shfl)
+ switch (p[1])
+ {
+ case 'w': shamt &= 15; break;
+ case 'h': shamt &= 7; break;
+ case 'b': shamt &= 3; break;
+ case 'n': shamt &= 1; break;
+ default: as_fatal (_("internal error: bad permutation pseudo-instruction %s"), op);
+ }
+ else
+ switch (p[1])
+ {
+ case 'w': shamt &= 31; break;
+ case 'h': shamt &= 15; break;
+ case 'b': shamt &= 7; break;
+ case 'n': shamt &= 3; break;
+ case 'p': shamt &= 1; break;
+ default: as_fatal (_("internal error: bad permutation pseudo-instruction %s"), op);
+ }
+ }
+
+ macro_build (NULL, insn, "d,s,>", rd, rs1, shamt);
+}
+
/* Expand RISC-V assembly macros into one or more instructions. */
static void
macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
@@ -1458,6 +1558,8 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
+ int rs3 = (ip->insn_opcode >> OP_SH_RS3) & OP_MASK_RS3;
+ int shamt = (ip->insn_opcode >> OP_SH_SHAMT) & OP_MASK_SHAMT;
int mask = ip->insn_mo->mask;
switch (mask)
@@ -1466,6 +1568,10 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
load_const (rd, imm_expr);
break;
+ case M_PERM:
+ perm (rd, rs1, ip->insn_mo->name);
+ break;
+
case M_LA:
case M_LLA:
/* Load the address of a symbol into a register. */
@@ -2265,6 +2371,17 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
s = expr_end;
continue;
+ case '|': /* Shift amount, 0 - (XLEN/2-1). */
+ my_getExpression (imm_expr, s);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ if ((unsigned long) imm_expr->X_add_number >= xlen/2)
+ as_bad (_("Improper shift amount (%lu)"),
+ (unsigned long) imm_expr->X_add_number);
+ INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
+ imm_expr->X_op = O_absent;
+ s = expr_end;
+ continue;
+
case '>': /* Shift amount, 0 - (XLEN-1). */
my_getExpression (imm_expr, s);
check_absolute_expr (ip, imm_expr, FALSE);
diff --git a/gas/testsuite/gas/riscv/attribute-draft-b.d b/gas/testsuite/gas/riscv/attribute-draft-b.d
new file mode 100644
index 0000000..0af5b71
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-draft-b.d
@@ -0,0 +1,6 @@
+#as: -march-attr -march=rv32ib_zba_zbb_zbc_zbe_zbf_zbm_zbp_zbr_zbs_zbt
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: .*b0p92_zba0p92_zbb0p92_zbc0p92_zbe0p92_zbf0p92_zbm0p92_zbp0p92_zbr0p92_zbs0p92_zbt0p92.*
diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
new file mode 100644
index 0000000..df691cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
@@ -0,0 +1,97 @@
+#as: -march=rv32ib_zbr_zbt
+#source: bitmanip-insns.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
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+[ ]+[0-9a-f]+:[ ]+08c5d533[ ]+unshfl[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0805d513[ ]+unshfli[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+08f5d513[ ]+unshfli[ ]+a0,a1,0xf
+[ ]+[0-9a-f]+:[ ]+08c5c533[ ]+pack[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+48c5c533[ ]+packu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5f533[ ]+packh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c5a533[ ]+xperm.n[ ]+a0,a1,a2
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+[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
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+[ ]+[0-9a-f]+:[ ]+61059513[ ]+crc32.b[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+61159513[ ]+crc32.h[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+61259513[ ]+crc32.w[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+61859513[ ]+crc32c.b[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+61959513[ ]+crc32c.h[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+61a59513[ ]+crc32c.w[ ]+a0,a1
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+[ ]+[0-9a-f]+:[ ]+28059513[ ]+sbseti[ ]+a0,a1,0x0
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+[ ]+[0-9a-f]+:[ ]+68059513[ ]+sbinvi[ ]+a0,a1,0x0
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+[ ]+[0-9a-f]+:[ ]+4805d513[ ]+sbexti[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+sbexti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+6eb61533[ ]+cmix[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+6eb65533[ ]+cmov[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+6405d513[ ]+fsri[ ]+a0,a1,a2,0x0
+[ ]+[0-9a-f]+:[ ]+65f5d513[ ]+fsri[ ]+a0,a1,a2,0x1f
+[ ]+[0-9a-f]+:[ ]+64d5d533[ ]+fsr[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+6405d513[ ]+fsri[ ]+a0,a1,a2,0x0
+[ ]+[0-9a-f]+:[ ]+65f5d513[ ]+fsri[ ]+a0,a1,a2,0x1f
+[ ]+[0-9a-f]+:[ ]+64d59533[ ]+fsl[ ]+a0,a1,a2,a3
diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
new file mode 100644
index 0000000..e4cf67c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
@@ -0,0 +1,177 @@
+#as: -march=rv64ib_zbr_zbt -defsym __64_bit__=1
+#source: bitmanip-insns.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
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diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
new file mode 100644
index 0000000..f9e7b8b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-32.d
@@ -0,0 +1,61 @@
+#as: -march=rv32ib
+#source: bitmanip-insns-pseudo.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
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+[ ]+[0-9a-f]+:[ ]+08659513[ ]+shfli[ ]+a0,a1,0x6
+[ ]+[0-9a-f]+:[ ]+08759513[ ]+shfli[ ]+a0,a1,0x7
+[ ]+[0-9a-f]+:[ ]+08859513[ ]+shfli[ ]+a0,a1,0x8
+[ ]+[0-9a-f]+:[ ]+08c59513[ ]+shfli[ ]+a0,a1,0xc
+[ ]+[0-9a-f]+:[ ]+08e59513[ ]+shfli[ ]+a0,a1,0xe
+[ ]+[0-9a-f]+:[ ]+08f59513[ ]+shfli[ ]+a0,a1,0xf
+[ ]+[0-9a-f]+:[ ]+0815d513[ ]+unshfli[ ]+a0,a1,0x1
+[ ]+[0-9a-f]+:[ ]+0825d513[ ]+unshfli[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+0835d513[ ]+unshfli[ ]+a0,a1,0x3
+[ ]+[0-9a-f]+:[ ]+0845d513[ ]+unshfli[ ]+a0,a1,0x4
+[ ]+[0-9a-f]+:[ ]+0865d513[ ]+unshfli[ ]+a0,a1,0x6
+[ ]+[0-9a-f]+:[ ]+0875d513[ ]+unshfli[ ]+a0,a1,0x7
+[ ]+[0-9a-f]+:[ ]+0885d513[ ]+unshfli[ ]+a0,a1,0x8
+[ ]+[0-9a-f]+:[ ]+08c5d513[ ]+unshfli[ ]+a0,a1,0xc
+[ ]+[0-9a-f]+:[ ]+08e5d513[ ]+unshfli[ ]+a0,a1,0xe
+[ ]+[0-9a-f]+:[ ]+08f5d513[ ]+unshfli[ ]+a0,a1,0xf
diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
new file mode 100644
index 0000000..0c25bae
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo-64.d
@@ -0,0 +1,84 @@
+#as: -march=rv64ib -defsym __64_bit__=1
+#source: bitmanip-insns-pseudo.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+zext.h[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6815d513[ ]+grevi[ ]+a0,a1,0x1
+[ ]+[0-9a-f]+:[ ]+6825d513[ ]+grevi[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+6835d513[ ]+grevi[ ]+a0,a1,0x3
+[ ]+[0-9a-f]+:[ ]+6845d513[ ]+grevi[ ]+a0,a1,0x4
+[ ]+[0-9a-f]+:[ ]+6865d513[ ]+grevi[ ]+a0,a1,0x6
+[ ]+[0-9a-f]+:[ ]+6875d513[ ]+grevi[ ]+a0,a1,0x7
+[ ]+[0-9a-f]+:[ ]+6885d513[ ]+grevi[ ]+a0,a1,0x8
+[ ]+[0-9a-f]+:[ ]+68c5d513[ ]+grevi[ ]+a0,a1,0xc
+[ ]+[0-9a-f]+:[ ]+68e5d513[ ]+grevi[ ]+a0,a1,0xe
+[ ]+[0-9a-f]+:[ ]+68f5d513[ ]+grevi[ ]+a0,a1,0xf
+[ ]+[0-9a-f]+:[ ]+6b05d513[ ]+grevi[ ]+a0,a1,0x30
+[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+grevi[ ]+a0,a1,0x38
+[ ]+[0-9a-f]+:[ ]+6bc5d513[ ]+grevi[ ]+a0,a1,0x3c
+[ ]+[0-9a-f]+:[ ]+6be5d513[ ]+grevi[ ]+a0,a1,0x3e
+[ ]+[0-9a-f]+:[ ]+6bf5d513[ ]+grevi[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+2815d513[ ]+gorci[ ]+a0,a1,0x1
+[ ]+[0-9a-f]+:[ ]+2825d513[ ]+gorci[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+2835d513[ ]+gorci[ ]+a0,a1,0x3
+[ ]+[0-9a-f]+:[ ]+2845d513[ ]+gorci[ ]+a0,a1,0x4
+[ ]+[0-9a-f]+:[ ]+2865d513[ ]+gorci[ ]+a0,a1,0x6
+[ ]+[0-9a-f]+:[ ]+2875d513[ ]+gorci[ ]+a0,a1,0x7
+[ ]+[0-9a-f]+:[ ]+2885d513[ ]+gorci[ ]+a0,a1,0x8
+[ ]+[0-9a-f]+:[ ]+28c5d513[ ]+gorci[ ]+a0,a1,0xc
+[ ]+[0-9a-f]+:[ ]+28e5d513[ ]+gorci[ ]+a0,a1,0xe
+[ ]+[0-9a-f]+:[ ]+28f5d513[ ]+gorci[ ]+a0,a1,0xf
+[ ]+[0-9a-f]+:[ ]+2b05d513[ ]+gorci[ ]+a0,a1,0x30
+[ ]+[0-9a-f]+:[ ]+2b85d513[ ]+gorci[ ]+a0,a1,0x38
+[ ]+[0-9a-f]+:[ ]+2bc5d513[ ]+gorci[ ]+a0,a1,0x3c
+[ ]+[0-9a-f]+:[ ]+2be5d513[ ]+gorci[ ]+a0,a1,0x3e
+[ ]+[0-9a-f]+:[ ]+2bf5d513[ ]+gorci[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+08159513[ ]+shfli[ ]+a0,a1,0x1
+[ ]+[0-9a-f]+:[ ]+08259513[ ]+shfli[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+08359513[ ]+shfli[ ]+a0,a1,0x3
+[ ]+[0-9a-f]+:[ ]+08459513[ ]+shfli[ ]+a0,a1,0x4
+[ ]+[0-9a-f]+:[ ]+08659513[ ]+shfli[ ]+a0,a1,0x6
+[ ]+[0-9a-f]+:[ ]+08759513[ ]+shfli[ ]+a0,a1,0x7
+[ ]+[0-9a-f]+:[ ]+09859513[ ]+shfli[ ]+a0,a1,0x18
+[ ]+[0-9a-f]+:[ ]+09c59513[ ]+shfli[ ]+a0,a1,0x1c
+[ ]+[0-9a-f]+:[ ]+09e59513[ ]+shfli[ ]+a0,a1,0x1e
+[ ]+[0-9a-f]+:[ ]+09f59513[ ]+shfli[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+0815d513[ ]+unshfli[ ]+a0,a1,0x1
+[ ]+[0-9a-f]+:[ ]+0825d513[ ]+unshfli[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+0835d513[ ]+unshfli[ ]+a0,a1,0x3
+[ ]+[0-9a-f]+:[ ]+0845d513[ ]+unshfli[ ]+a0,a1,0x4
+[ ]+[0-9a-f]+:[ ]+0865d513[ ]+unshfli[ ]+a0,a1,0x6
+[ ]+[0-9a-f]+:[ ]+0875d513[ ]+unshfli[ ]+a0,a1,0x7
+[ ]+[0-9a-f]+:[ ]+0985d513[ ]+unshfli[ ]+a0,a1,0x18
+[ ]+[0-9a-f]+:[ ]+09c5d513[ ]+unshfli[ ]+a0,a1,0x1c
+[ ]+[0-9a-f]+:[ ]+09e5d513[ ]+unshfli[ ]+a0,a1,0x1e
+[ ]+[0-9a-f]+:[ ]+09f5d513[ ]+unshfli[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+0805853b[ ]+zext.w[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6905d513[ ]+grevi[ ]+a0,a1,0x10
+[ ]+[0-9a-f]+:[ ]+6985d513[ ]+grevi[ ]+a0,a1,0x18
+[ ]+[0-9a-f]+:[ ]+69c5d513[ ]+grevi[ ]+a0,a1,0x1c
+[ ]+[0-9a-f]+:[ ]+69e5d513[ ]+grevi[ ]+a0,a1,0x1e
+[ ]+[0-9a-f]+:[ ]+69f5d513[ ]+grevi[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+6a05d513[ ]+grevi[ ]+a0,a1,0x20
+[ ]+[0-9a-f]+:[ ]+2905d513[ ]+gorci[ ]+a0,a1,0x10
+[ ]+[0-9a-f]+:[ ]+2985d513[ ]+gorci[ ]+a0,a1,0x18
+[ ]+[0-9a-f]+:[ ]+29c5d513[ ]+gorci[ ]+a0,a1,0x1c
+[ ]+[0-9a-f]+:[ ]+29e5d513[ ]+gorci[ ]+a0,a1,0x1e
+[ ]+[0-9a-f]+:[ ]+29f5d513[ ]+gorci[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+2a05d513[ ]+gorci[ ]+a0,a1,0x20
+[ ]+[0-9a-f]+:[ ]+08859513[ ]+shfli[ ]+a0,a1,0x8
+[ ]+[0-9a-f]+:[ ]+08c59513[ ]+shfli[ ]+a0,a1,0xc
+[ ]+[0-9a-f]+:[ ]+08e59513[ ]+shfli[ ]+a0,a1,0xe
+[ ]+[0-9a-f]+:[ ]+08f59513[ ]+shfli[ ]+a0,a1,0xf
+[ ]+[0-9a-f]+:[ ]+09059513[ ]+shfli[ ]+a0,a1,0x10
+[ ]+[0-9a-f]+:[ ]+0885d513[ ]+unshfli[ ]+a0,a1,0x8
+[ ]+[0-9a-f]+:[ ]+08c5d513[ ]+unshfli[ ]+a0,a1,0xc
+[ ]+[0-9a-f]+:[ ]+08e5d513[ ]+unshfli[ ]+a0,a1,0xe
+[ ]+[0-9a-f]+:[ ]+08f5d513[ ]+unshfli[ ]+a0,a1,0xf
+[ ]+[0-9a-f]+:[ ]+0905d513[ ]+unshfli[ ]+a0,a1,0x10
diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-pseudo.s b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo.s
new file mode 100644
index 0000000..4c38e0a2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bitmanip-insns-pseudo.s
@@ -0,0 +1,85 @@
+ zext.h a0, a1 /* ZBB */
+
+ rev.p a0, a1
+ rev2.n a0, a1
+ rev.n a0, a1
+ rev4.b a0, a1
+ rev2.b a0, a1
+ rev.b a0, a1
+ rev8.h a0, a1
+ rev4.h a0, a1
+ rev2.h a0, a1
+ rev.h a0, a1
+ rev16 a0, a1
+ rev8 a0, a1 /* ZBB */
+ rev4 a0, a1
+ rev2 a0, a1
+ rev a0, a1
+
+ orc.p a0, a1
+ orc2.n a0, a1
+ orc.n a0, a1
+ orc4.b a0, a1
+ orc2.b a0, a1
+ orc.b a0, a1 /* ZBB */
+ orc8.h a0, a1
+ orc4.h a0, a1
+ orc2.h a0, a1
+ orc.h a0, a1
+ orc16 a0, a1
+ orc8 a0, a1
+ orc4 a0, a1
+ orc2 a0, a1
+ orc a0, a1
+
+ zip.n a0, a1
+ zip2.b a0, a1
+ zip.b a0, a1
+ zip4.h a0, a1
+ zip2.h a0, a1
+ zip.h a0, a1
+ zip8 a0, a1
+ zip4 a0, a1
+ zip2 a0, a1
+ zip a0, a1
+
+ unzip.n a0, a1
+ unzip2.b a0, a1
+ unzip.b a0, a1
+ unzip4.h a0, a1
+ unzip2.h a0, a1
+ unzip.h a0, a1
+ unzip8 a0, a1
+ unzip4 a0, a1
+ unzip2 a0, a1
+ unzip a0, a1
+
+.ifdef __64_bit__
+ zext.w a0, a1 /* ZBB */
+
+ rev16.w a0, a1
+ rev8.w a0, a1
+ rev4.w a0, a1
+ rev2.w a0, a1
+ rev.w a0, a1
+ rev32 a0, a1
+
+ orc16.w a0, a1
+ orc8.w a0, a1
+ orc4.w a0, a1
+ orc2.w a0, a1
+ orc.w a0, a1
+ orc32 a0, a1
+
+ zip8.w a0, a1
+ zip4.w a0, a1
+ zip2.w a0, a1
+ zip.w a0, a1
+ zip16 a0, a1
+
+ unzip8.w a0, a1
+ unzip4.w a0, a1
+ unzip2.w a0, a1
+ unzip.w a0, a1
+ unzip16 a0, a1
+.endif
diff --git a/gas/testsuite/gas/riscv/bitmanip-insns.s b/gas/testsuite/gas/riscv/bitmanip-insns.s
new file mode 100644
index 0000000..f39faeb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bitmanip-insns.s
@@ -0,0 +1,204 @@
+ # ZBA
+ sh1add a0, a1, a2
+ sh2add a0, a1, a2
+ sh3add a0, a1, a2
+.ifdef __64_bit__
+ slliu.w a0, a1, 0
+ slliu.w a0, a1, 63
+ addu.w a0, a1, a2
+ sh1addu.w a0, a1, a2
+ sh2addu.w a0, a1, a2
+ sh3addu.w a0, a1, a2
+.endif
+
+ # ZBB
+ clz a0, a1
+ ctz a0, a1
+ pcnt a0, a1
+ min a0, a1, a2
+ max a0, a1, a2
+ minu a0, a1, a2
+ maxu a0, a1, a2
+ sext.b a0, a1
+ sext.h a0, a1
+ andn a0, a1, a2 /* ZBB or ZBP */
+ orn a0, a1, a2 /* ZBB or ZBP */
+ xor a0, a1, a2 /* ZBB or ZBP */
+ rori a0, a1, 0 /* ZBB or ZBP */
+ rori a0, a1, 31 /* ZBB or ZBP */
+ ror a0, a1, a2 /* ZBB or ZBP */
+ ror a0, a1, 0 /* ZBB or ZBP */
+ ror a0, a1, 31 /* ZBB or ZBP */
+ rol a0, a1, a2 /* ZBB or ZBP */
+.ifdef __64_bit__
+ clzw a0, a1
+ ctzw a0, a1
+ pcntw a0, a1
+ rori a0, a1, 63 /* ZBB or ZBP */
+ ror a0, a1, 63 /* ZBB or ZBP */
+ roriw a0, a1, 0 /* ZBB or ZBP */
+ roriw a0, a1, 31 /* ZBB or ZBP */
+ rorw a0, a1, a2 /* ZBB or ZBP */
+ rorw a0, a1, 0 /* ZBB or ZBP */
+ rorw a0, a1, 31 /* ZBB or ZBP */
+ rolw a0, a1, a2 /* ZBB or ZBP */
+.endif
+
+ # ZBP
+ gorci a0, a1, 0
+ gorci a0, a1, 31
+ gorc a0, a1, a2
+ gorc a0, a1, 0
+ gorc a0, a1, 31
+ grevi a0, a1, 0
+ grevi a0, a1, 31
+ grev a0, a1, a2
+ grev a0, a1, 0
+ grev a0, a1, 31
+ shfli a0, a1, 0
+ shfli a0, a1, 15
+ shfl a0, a1, a2
+ shfl a0, a1, 0
+ shfl a0, a1, 15
+ unshfli a0, a1, 0
+ unshfli a0, a1, 15
+ unshfl a0, a1, a2
+ unshfl a0, a1, 0
+ unshfl a0, a1, 15
+ pack a0, a1, a2 /* ZBF or ZBP */
+ packu a0, a1, a2
+ packh a0, a1, a2 /* ZBF or ZBP */
+ xperm.n a0, a1, a2
+ xperm.b a0, a1, a2
+ xperm.h a0, a1, a2
+.ifdef __64_bit__
+ gorci a0, a1, 63
+ gorc a0, a1, 63
+ grevi a0, a1, 63
+ grev a0, a1, 63
+ shfli a0, a1, 31
+ shfl a0, a1, 31
+ unshfli a0, a1, 31
+ unshfl a0, a1, 31
+ gorciw a0, a1, 0
+ gorciw a0, a1, 31
+ gorcw a0, a1, a2
+ gorcw a0, a1, 0
+ gorcw a0, a1, 31
+ greviw a0, a1, 0
+ greviw a0, a1, 31
+ grevw a0, a1, a2
+ grevw a0, a1, 0
+ grevw a0, a1, 31
+ shflw a0, a1, a2
+ unshflw a0, a1, a2
+ packw a0, a1, a2 /* ZBF or ZBP */
+ packuw a0, a1, a2
+ xperm.w a0, a1, a2
+.endif
+
+ # ZBF
+ bfp a0, a1, a2
+.ifdef __64_bit__
+ bfpw a0, a1, a2
+.endif
+
+ # ZBC
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
+ clmulr a0, a1, a2
+
+ # ZBE
+ bdep a0, a1, a2
+ bext a0, a1, a2
+.ifdef __64_bit__
+ bdepw a0, a1, a2
+ bextw a0, a1, a2
+.endif
+
+ # ZBM
+.ifdef __64_bit__
+ bmatflip a0, a1
+ bmator a0, a1, a2
+ bmatxor a0, a1, a2
+.endif
+
+ # ZBR
+ crc32.b a0, a1
+ crc32.h a0, a1
+ crc32.w a0, a1
+ crc32c.b a0, a1
+ crc32c.h a0, a1
+ crc32c.w a0, a1
+.ifdef __64_bit__
+ crc32.d a0, a1
+ crc32c.d a0, a1
+.endif
+
+ # ZBS
+ sbclri a0, a1, 0
+ sbclri a0, a1, 31
+ sbclr a0, a1, a2
+ sbclr a0, a1, 0
+ sbclr a0, a1, 31
+ sbseti a0, a1, 0
+ sbseti a0, a1, 31
+ sbset a0, a1, a2
+ sbset a0, a1, 0
+ sbset a0, a1, 31
+ sbinvi a0, a1, 0
+ sbinvi a0, a1, 31
+ sbinv a0, a1, a2
+ sbinv a0, a1, 0
+ sbinv a0, a1, 31
+ sbexti a0, a1, 0
+ sbexti a0, a1, 31
+ sbext a0, a1, a2
+ sbext a0, a1, 0
+ sbext a0, a1, 31
+.ifdef __64_bit__
+ sbclri a0, a1, 63
+ sbclr a0, a1, 63
+ sbseti a0, a1, 63
+ sbset a0, a1, 63
+ sbinvi a0, a1, 63
+ sbinv a0, a1, 63
+ sbexti a0, a1, 63
+ sbext a0, a1, 63
+ sbclriw a0, a1, 0
+ sbclriw a0, a1, 31
+ sbclrw a0, a1, a2
+ sbclrw a0, a1, 0
+ sbclrw a0, a1, 31
+ sbsetiw a0, a1, 0
+ sbsetiw a0, a1, 31
+ sbsetw a0, a1, a2
+ sbsetw a0, a1, 0
+ sbsetw a0, a1, 31
+ sbinviw a0, a1, 0
+ sbinviw a0, a1, 31
+ sbinvw a0, a1, a2
+ sbinvw a0, a1, 0
+ sbinvw a0, a1, 31
+ sbextw a0, a1, a2
+.endif
+
+ # ZBT
+ cmix a0, a1, a2, a3
+ cmov a0, a1, a2, a3
+ fsri a0, a1, a2, 0
+ fsri a0, a1, a2, 31
+ fsr a0, a1, a2, a3
+ fsr a0, a1, a2, 0
+ fsr a0, a1, a2, 31
+ fsl a0, a1, a2, a3
+.ifdef __64_bit__
+ fsri a0, a1, a2, 63
+ fsr a0, a1, a2, 63
+ fsriw a0, a1, a2, 0
+ fsriw a0, a1, a2, 31
+ fsrw a0, a1, a2, a3
+ fsrw a0, a1, a2, 0
+ fsrw a0, a1, a2, 31
+ fslw a0, a1, a2, a3
+.endif
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 158de32..e53b986 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -189,6 +189,197 @@
#define MASK_REMW 0xfe00707f
#define MATCH_REMUW 0x200703b
#define MASK_REMUW 0xfe00707f
+#define MATCH_ANDN 0x40007033
+#define MASK_ANDN 0xfe00707f
+#define MATCH_ORN 0x40006033
+#define MASK_ORN 0xfe00707f
+#define MATCH_XNOR 0x40004033
+#define MASK_XNOR 0xfe00707f
+#define MATCH_ROL 0x60001033
+#define MASK_ROL 0xfe00707f
+#define MATCH_ROR 0x60005033
+#define MASK_ROR 0xfe00707f
+#define MATCH_SBCLR 0x48001033
+#define MASK_SBCLR 0xfe00707f
+#define MATCH_SBSET 0x28001033
+#define MASK_SBSET 0xfe00707f
+#define MATCH_SBINV 0x68001033
+#define MASK_SBINV 0xfe00707f
+#define MATCH_SBEXT 0x48005033
+#define MASK_SBEXT 0xfe00707f
+#define MATCH_GORC 0x28005033
+#define MASK_GORC 0xfe00707f
+#define MATCH_GREV 0x68005033
+#define MASK_GREV 0xfe00707f
+#define MATCH_RORI 0x60005013
+#define MASK_RORI 0xfc00707f
+#define MATCH_SBCLRI 0x48001013
+#define MASK_SBCLRI 0xfc00707f
+#define MATCH_SBSETI 0x28001013
+#define MASK_SBSETI 0xfc00707f
+#define MATCH_SBINVI 0x68001013
+#define MASK_SBINVI 0xfc00707f
+#define MATCH_SBEXTI 0x48005013
+#define MASK_SBEXTI 0xfc00707f
+#define MATCH_GORCI 0x28005013
+#define MASK_GORCI 0xfc00707f
+#define MATCH_GREVI 0x68005013
+#define MASK_GREVI 0xfc00707f
+#define MATCH_CMIX 0x6001033
+#define MASK_CMIX 0x600707f
+#define MATCH_CMOV 0x6005033
+#define MASK_CMOV 0x600707f
+#define MATCH_FSL 0x4001033
+#define MASK_FSL 0x600707f
+#define MATCH_FSR 0x4005033
+#define MASK_FSR 0x600707f
+#define MATCH_FSRI 0x4005013
+#define MASK_FSRI 0x400707f
+#define MATCH_CLZ 0x60001013
+#define MASK_CLZ 0xfff0707f
+#define MATCH_CTZ 0x60101013
+#define MASK_CTZ 0xfff0707f
+#define MATCH_PCNT 0x60201013
+#define MASK_PCNT 0xfff0707f
+#define MATCH_SEXT_B 0x60401013
+#define MASK_SEXT_B 0xfff0707f
+#define MATCH_SEXT_H 0x60501013
+#define MASK_SEXT_H 0xfff0707f
+#define MATCH_CRC32_B 0x61001013
+#define MASK_CRC32_B 0xfff0707f
+#define MATCH_CRC32_H 0x61101013
+#define MASK_CRC32_H 0xfff0707f
+#define MATCH_CRC32_W 0x61201013
+#define MASK_CRC32_W 0xfff0707f
+#define MATCH_CRC32C_B 0x61801013
+#define MASK_CRC32C_B 0xfff0707f
+#define MATCH_CRC32C_H 0x61901013
+#define MASK_CRC32C_H 0xfff0707f
+#define MATCH_CRC32C_W 0x61a01013
+#define MASK_CRC32C_W 0xfff0707f
+#define MATCH_SH1ADD 0x20002033
+#define MASK_SH1ADD 0xfe00707f
+#define MATCH_SH2ADD 0x20004033
+#define MASK_SH2ADD 0xfe00707f
+#define MATCH_SH3ADD 0x20006033
+#define MASK_SH3ADD 0xfe00707f
+#define MATCH_CLMUL 0xa001033
+#define MASK_CLMUL 0xfe00707f
+#define MATCH_CLMULR 0xa002033
+#define MASK_CLMULR 0xfe00707f
+#define MATCH_CLMULH 0xa003033
+#define MASK_CLMULH 0xfe00707f
+#define MATCH_MIN 0xa004033
+#define MASK_MIN 0xfe00707f
+#define MATCH_MAX 0xa006033
+#define MASK_MAX 0xfe00707f
+#define MATCH_MINU 0xa005033
+#define MASK_MINU 0xfe00707f
+#define MATCH_MAXU 0xa007033
+#define MASK_MAXU 0xfe00707f
+#define MATCH_SHFL 0x8001033
+#define MASK_SHFL 0xfe00707f
+#define MATCH_UNSHFL 0x8005033
+#define MASK_UNSHFL 0xfe00707f
+#define MATCH_BEXT 0x8006033
+#define MASK_BEXT 0xfe00707f
+#define MATCH_BDEP 0x48006033
+#define MASK_BDEP 0xfe00707f
+#define MATCH_PACK 0x8004033
+#define MASK_PACK 0xfe00707f
+#define MATCH_PACKU 0x48004033
+#define MASK_PACKU 0xfe00707f
+#define MATCH_PACKH 0x8007033
+#define MASK_PACKH 0xfe00707f
+#define MATCH_BFP 0x48007033
+#define MASK_BFP 0xfe00707f
+#define MATCH_SHFLI 0x8001013
+#define MASK_SHFLI 0xfe00707f
+#define MATCH_UNSHFLI 0x8005013
+#define MASK_UNSHFLI 0xfe00707f
+#define MATCH_BMATFLIP 0x60301013
+#define MASK_BMATFLIP 0xfff0707f
+#define MATCH_CRC32_D 0x61301013
+#define MASK_CRC32_D 0xfff0707f
+#define MATCH_CRC32C_D 0x61b01013
+#define MASK_CRC32C_D 0xfff0707f
+#define MATCH_BMATOR 0x8003033
+#define MASK_BMATOR 0xfe00707f
+#define MATCH_BMATXOR 0x48003033
+#define MASK_BMATXOR 0xfe00707f
+#define MATCH_SLLIU_W 0x800101b
+#define MASK_SLLIU_W 0xfc00707f
+#define MATCH_ADDU_W 0x800003b
+#define MASK_ADDU_W 0xfe00707f
+#define MATCH_ROLW 0x6000103b
+#define MASK_ROLW 0xfe00707f
+#define MATCH_RORW 0x6000503b
+#define MASK_RORW 0xfe00707f
+#define MATCH_SBCLRW 0x4800103b
+#define MASK_SBCLRW 0xfe00707f
+#define MATCH_SBSETW 0x2800103b
+#define MASK_SBSETW 0xfe00707f
+#define MATCH_SBINVW 0x6800103b
+#define MASK_SBINVW 0xfe00707f
+#define MATCH_SBEXTW 0x4800503b
+#define MASK_SBEXTW 0xfe00707f
+#define MATCH_GORCW 0x2800503b
+#define MASK_GORCW 0xfe00707f
+#define MATCH_GREVW 0x6800503b
+#define MASK_GREVW 0xfe00707f
+#define MATCH_RORIW 0x6000501b
+#define MASK_RORIW 0xfe00707f
+#define MATCH_SBCLRIW 0x4800101b
+#define MASK_SBCLRIW 0xfe00707f
+#define MATCH_SBSETIW 0x2800101b
+#define MASK_SBSETIW 0xfe00707f
+#define MATCH_SBINVIW 0x6800101b
+#define MASK_SBINVIW 0xfe00707f
+#define MATCH_GORCIW 0x2800501b
+#define MASK_GORCIW 0xfe00707f
+#define MATCH_GREVIW 0x6800501b
+#define MASK_GREVIW 0xfe00707f
+#define MATCH_FSLW 0x400103b
+#define MASK_FSLW 0x600707f
+#define MATCH_FSRW 0x400503b
+#define MASK_FSRW 0x600707f
+#define MATCH_FSRIW 0x400501b
+#define MASK_FSRIW 0x600707f
+#define MATCH_CLZW 0x6000101b
+#define MASK_CLZW 0xfff0707f
+#define MATCH_CTZW 0x6010101b
+#define MASK_CTZW 0xfff0707f
+#define MATCH_PCNTW 0x6020101b
+#define MASK_PCNTW 0xfff0707f
+#define MATCH_SH1ADDU_W 0x2000203b
+#define MASK_SH1ADDU_W 0xfe00707f
+#define MATCH_SH2ADDU_W 0x2000403b
+#define MASK_SH2ADDU_W 0xfe00707f
+#define MATCH_SH3ADDU_W 0x2000603b
+#define MASK_SH3ADDU_W 0xfe00707f
+#define MATCH_SHFLW 0x800103b
+#define MASK_SHFLW 0xfe00707f
+#define MATCH_UNSHFLW 0x800503b
+#define MASK_UNSHFLW 0xfe00707f
+#define MATCH_BEXTW 0x800603b
+#define MASK_BEXTW 0xfe00707f
+#define MATCH_BDEPW 0x4800603b
+#define MASK_BDEPW 0xfe00707f
+#define MATCH_PACKW 0x800403b
+#define MASK_PACKW 0xfe00707f
+#define MATCH_PACKUW 0x4800403b
+#define MASK_PACKUW 0xfe00707f
+#define MATCH_BFPW 0x4800703b
+#define MASK_BFPW 0xfe00707f
+#define MATCH_XPERMN 0x28002033
+#define MASK_XPERMN 0xfe00707f
+#define MATCH_XPERMB 0x28004033
+#define MASK_XPERMB 0xfe00707f
+#define MATCH_XPERMH 0x28003033
+#define MASK_XPERMH 0xfe00707f
+#define MATCH_XPERMW 0x28000033
+#define MASK_XPERMW 0xfe00707f
+
#define MATCH_AMOADD_W 0x202f
#define MASK_AMOADD_W 0xf800707f
#define MATCH_AMOXOR_W 0x2000202f
@@ -927,6 +1118,102 @@ DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
+DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
+DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
+DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
+DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
+DECLARE_INSN(sbclr, MATCH_SBCLR, MASK_SBCLR)
+DECLARE_INSN(sbset, MATCH_SBSET, MASK_SBSET)
+DECLARE_INSN(sbinv, MATCH_SBINV, MASK_SBINV)
+DECLARE_INSN(sbext, MATCH_SBEXT, MASK_SBEXT)
+DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
+DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
+DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
+DECLARE_INSN(sbclri, MATCH_SBCLRI, MASK_SBCLRI)
+DECLARE_INSN(sbseti, MATCH_SBSETI, MASK_SBSETI)
+DECLARE_INSN(sbinvi, MATCH_SBINVI, MASK_SBINVI)
+DECLARE_INSN(sbexti, MATCH_SBEXTI, MASK_SBEXTI)
+DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
+DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
+DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
+DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
+DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL)
+DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
+DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
+DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
+DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
+DECLARE_INSN(pcnt, MATCH_PCNT, MASK_PCNT)
+DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
+DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
+DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
+DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H)
+DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W)
+DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B)
+DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H)
+DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W)
+DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
+DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
+DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
+DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
+DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
+DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
+DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
+DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
+DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
+DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
+DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
+DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
+DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
+DECLARE_INSN(bdep, MATCH_BDEP, MASK_BDEP)
+DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
+DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
+DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
+DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
+DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
+DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
+DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
+DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
+DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
+DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
+DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
+DECLARE_INSN(slliu_w, MATCH_SLLIU_W, MASK_SLLIU_W)
+DECLARE_INSN(addu_w, MATCH_ADDU_W, MASK_ADDU_W)
+DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
+DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
+DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW)
+DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW)
+DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW)
+DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW)
+DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
+DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
+DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
+DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW)
+DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW)
+DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW)
+DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
+DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
+DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
+DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
+DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
+DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
+DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
+DECLARE_INSN(pcntw, MATCH_PCNTW, MASK_PCNTW)
+DECLARE_INSN(sh1addu_w, MATCH_SH1ADDU_W, MASK_SH1ADDU_W)
+DECLARE_INSN(sh2addu_w, MATCH_SH2ADDU_W, MASK_SH2ADDU_W)
+DECLARE_INSN(sh3addu_w, MATCH_SH3ADDU_W, MASK_SH3ADDU_W)
+DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
+DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
+DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW)
+DECLARE_INSN(bdepw, MATCH_BDEPW, MASK_BDEPW)
+DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
+DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
+DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
+DECLARE_INSN(xperm.n, MATCH_XPERMN, MASK_XPERMN)
+DECLARE_INSN(xperm.b, MATCH_XPERMB, MASK_XPERMB)
+DECLARE_INSN(xperm.h, MATCH_XPERMH, MASK_XPERMH)
+DECLARE_INSN(xperm.w, MATCH_XPERMW, MASK_XPERMW)
+
DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 1949072..0255feb 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -307,10 +307,23 @@ enum riscv_insn_class
INSN_CLASS_F,
INSN_CLASS_D,
INSN_CLASS_Q,
+ INSN_CLASS_B,
INSN_CLASS_F_AND_C,
INSN_CLASS_D_AND_C,
INSN_CLASS_ZICSR,
INSN_CLASS_ZIFENCEI,
+ INSN_CLASS_B_OR_ZBA,
+ INSN_CLASS_B_OR_ZBB,
+ INSN_CLASS_B_OR_ZBC,
+ INSN_CLASS_B_OR_ZBE,
+ INSN_CLASS_B_OR_ZBF,
+ INSN_CLASS_B_OR_ZBM,
+ INSN_CLASS_B_OR_ZBP,
+ INSN_CLASS_ZBR,
+ INSN_CLASS_B_OR_ZBS,
+ INSN_CLASS_ZBT,
+ INSN_CLASS_B_OR_ZBB_OR_ZBP,
+ INSN_CLASS_B_OR_ZBF_OR_ZBP
};
/* This structure holds information for a particular instruction. */
@@ -353,7 +366,8 @@ enum riscv_isa_spec_class
ISA_SPEC_CLASS_2P2,
ISA_SPEC_CLASS_20190608,
- ISA_SPEC_CLASS_20191213
+ ISA_SPEC_CLASS_20191213,
+ ISA_SPEC_CLASS_DRAFT
};
#define RISCV_UNKNOWN_VERSION -1
@@ -484,6 +498,7 @@ enum
M_ZEXTW,
M_SEXTB,
M_SEXTH,
+ M_PERM,
M_NUM_MACROS
};
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index ca3b110..aaa8060 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -245,6 +245,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
case '>':
print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f);
break;
+ case '|':
case '<':
print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
break;
@@ -285,6 +286,11 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
break;
+ case 'r':
+ print (info->stream, "%s",
+ riscv_gpr_names[EXTRACT_OPERAND (RS3, l)]);
+ break;
+
case 'u':
print (info->stream, "0x%x",
(unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
@@ -348,6 +354,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l));
break;
+ case '|':
case '<':
print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l));
break;
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index f90d717..bf8b27a 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -238,10 +238,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"mv", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
{"move", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
{"move", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
-{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
-{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
{"zext.b", 0, INSN_CLASS_I, "d,s", MATCH_ANDI | ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
-{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
{"andi", 0, INSN_CLASS_C, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
{"andi", 0, INSN_CLASS_I, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
{"and", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
@@ -374,7 +371,6 @@ const struct riscv_opcode riscv_opcodes[] =
{"sd", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"sd", 64, INSN_CLASS_I, "t,q(s)", MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE },
{"sd", 64, INSN_CLASS_I, "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO },
-{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
{"sext.w", 64, INSN_CLASS_C, "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
{"sext.w", 64, INSN_CLASS_I, "d,s", MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS },
{"addiw", 64, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
@@ -502,6 +498,213 @@ const struct riscv_opcode riscv_opcodes[] =
{"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 },
{"remuw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
+/* Bitmanip instruction subset */
+{"sh1add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
+{"sh2add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
+{"sh3add", 0, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
+{"slliu.w", 64, INSN_CLASS_B_OR_ZBA, "d,s,>", MATCH_SLLIU_W, MASK_SLLIU_W, match_opcode, 0 },
+{"zext.w", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_ADDU_W, MASK_ADDU_W | MASK_RS2, match_opcode, INSN_ALIAS },
+{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
+{"addu.w", 64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_ADDU_W, MASK_ADDU_W, match_opcode, 0 },
+{"sh1addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH1ADDU_W, MASK_SH1ADDU_W, match_opcode, 0 },
+{"sh2addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH2ADDU_W, MASK_SH2ADDU_W, match_opcode, 0 },
+{"sh3addu.w",64, INSN_CLASS_B_OR_ZBA, "d,s,t", MATCH_SH3ADDU_W, MASK_SH3ADDU_W, match_opcode, 0 },
+
+{"clz", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
+{"ctz", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
+{"pcnt", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PCNT, MASK_PCNT, match_opcode, 0 },
+{"min", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
+{"max", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
+{"minu", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
+{"maxu", 0, INSN_CLASS_B_OR_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
+{"sext.b", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
+{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
+{"sext.h", 0, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
+{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
+{"zext.h", 32, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, INSN_ALIAS },
+{"zext.h", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, INSN_ALIAS },
+{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
+{"andn", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
+{"orn", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
+{"xnor", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
+{"rori", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
+{"ror", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
+{"ror", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
+{"rol", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
+{"clzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
+{"ctzw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
+{"pcntw", 64, INSN_CLASS_B_OR_ZBB, "d,s", MATCH_PCNTW, MASK_PCNTW, match_opcode, 0 },
+{"roriw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+{"rorw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
+{"rorw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
+{"rolw", 64, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
+
+{"gorci", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, 0 },
+{"grevi", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GREVI, MASK_GREVI, match_opcode, 0 },
+{"gorc", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GORC, MASK_GORC, match_opcode, 0 },
+{"gorc", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GORCI, MASK_GORCI, match_opcode, INSN_ALIAS },
+{"grev", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GREV, MASK_GREV, match_opcode, 0 },
+{"grev", 0, INSN_CLASS_B_OR_ZBP, "d,s,>", MATCH_GREVI, MASK_GREVI, match_opcode, INSN_ALIAS },
+{"shfli", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_SHFLI, MASK_SHFLI, match_opcode, 0 },
+{"unshfli", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, 0 },
+{"shfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SHFL, MASK_SHFL, match_opcode, 0 },
+{"shfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_SHFLI, MASK_SHFLI, match_opcode, INSN_ALIAS },
+{"unshfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_UNSHFL, MASK_UNSHFL, match_opcode, 0 },
+{"unshfl", 0, INSN_CLASS_B_OR_ZBP, "d,s,|", MATCH_UNSHFLI, MASK_UNSHFLI, match_opcode, INSN_ALIAS },
+{"pack", 0, INSN_CLASS_B_OR_ZBF_OR_ZBP, "d,s,t", MATCH_PACK, MASK_PACK, match_opcode, 0 },
+{"packu", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_PACKU, MASK_PACKU, match_opcode, 0 },
+{"packh", 0, INSN_CLASS_B_OR_ZBF_OR_ZBP, "d,s,t", MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
+{"xperm.n", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMN, MASK_XPERMN, match_opcode, 0 },
+{"xperm.b", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMB, MASK_XPERMB, match_opcode, 0 },
+{"xperm.h", 0, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMH, MASK_XPERMH, match_opcode, 0 },
+{"gorciw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, 0 },
+{"greviw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, 0 },
+{"gorcw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GORCW, MASK_GORCW, match_opcode, 0 },
+{"gorcw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GORCIW, MASK_GORCIW, match_opcode, INSN_ALIAS },
+{"grevw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_GREVW, MASK_GREVW, match_opcode, 0 },
+{"grevw", 64, INSN_CLASS_B_OR_ZBP, "d,s,<", MATCH_GREVIW, MASK_GREVIW, match_opcode, INSN_ALIAS },
+{"shflw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_SHFLW, MASK_SHFLW, match_opcode, 0 },
+{"unshflw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_UNSHFLW, MASK_UNSHFLW, match_opcode, 0 },
+{"packw", 64, INSN_CLASS_B_OR_ZBF_OR_ZBP, "d,s,t", MATCH_PACKW, MASK_PACKW, match_opcode, 0 },
+{"packuw", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_PACKUW, MASK_PACKUW, match_opcode, 0 },
+{"xperm.w", 64, INSN_CLASS_B_OR_ZBP, "d,s,t", MATCH_XPERMW, MASK_XPERMW, match_opcode, 0 },
+
+{"bfp", 0, INSN_CLASS_B_OR_ZBF, "d,s,t", MATCH_BFP, MASK_BFP, match_opcode, 0 },
+{"bfpw", 64, INSN_CLASS_B_OR_ZBF, "d,s,t", MATCH_BFPW, MASK_BFPW, match_opcode, 0 },
+
+{"clmul", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
+{"clmulh", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
+{"clmulr", 0, INSN_CLASS_B_OR_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
+
+{"bdep", 0, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BDEP, MASK_BDEP, match_opcode, 0 },
+{"bext", 0, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
+{"bdepw", 64, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BDEPW, MASK_BDEPW, match_opcode, 0 },
+{"bextw", 64, INSN_CLASS_B_OR_ZBE, "d,s,t", MATCH_BEXTW, MASK_BEXTW, match_opcode, 0 },
+
+{"bmatflip", 64, INSN_CLASS_B_OR_ZBM, "d,s", MATCH_BMATFLIP, MASK_BMATFLIP, match_opcode, 0 },
+{"bmator", 64, INSN_CLASS_B_OR_ZBM, "d,s,t", MATCH_BMATOR, MASK_BMATOR, match_opcode, 0 },
+{"bmatxor", 64, INSN_CLASS_B_OR_ZBM, "d,s,t", MATCH_BMATXOR, MASK_BMATXOR, match_opcode, 0 },
+
+{"crc32.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_B, MASK_CRC32_B, match_opcode, 0 },
+{"crc32.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_H, MASK_CRC32_H, match_opcode, 0 },
+{"crc32.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_W, MASK_CRC32_W, match_opcode, 0 },
+{"crc32c.b", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_B, MASK_CRC32C_B, match_opcode, 0 },
+{"crc32c.h", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_H, MASK_CRC32C_H, match_opcode, 0 },
+{"crc32c.w", 0, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_W, MASK_CRC32C_W, match_opcode, 0 },
+{"crc32.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32_D, MASK_CRC32_D, match_opcode, 0 },
+{"crc32c.d", 64, INSN_CLASS_ZBR, "d,s", MATCH_CRC32C_D, MASK_CRC32C_D, match_opcode, 0 },
+
+{"sbclri", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, 0 },
+{"sbseti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, 0 },
+{"sbinvi", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, 0 },
+{"sbexti", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, 0 },
+{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLR, MASK_SBCLR, match_opcode, 0 },
+{"sbclr", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBCLRI, MASK_SBCLRI, match_opcode, INSN_ALIAS },
+{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBSET, MASK_SBSET, match_opcode, 0 },
+{"sbset", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBSETI, MASK_SBSETI, match_opcode, INSN_ALIAS },
+{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBINV, MASK_SBINV, match_opcode, 0 },
+{"sbinv", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBINVI, MASK_SBINVI, match_opcode, INSN_ALIAS },
+{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXT, MASK_SBEXT, match_opcode, 0 },
+{"sbext", 0, INSN_CLASS_B_OR_ZBS, "d,s,>", MATCH_SBEXTI, MASK_SBEXTI, match_opcode, INSN_ALIAS },
+{"sbclriw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, 0 },
+{"sbsetiw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBSETIW, MASK_SBSETIW, match_opcode, 0 },
+{"sbinviw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBINVIW, MASK_SBINVIW, match_opcode, 0 },
+{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBCLRW, MASK_SBCLRW, match_opcode, 0 },
+{"sbclrw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBCLRIW, MASK_SBCLRIW, match_opcode, INSN_ALIAS },
+{"sbsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBSETW, MASK_SBSETW, match_opcode, 0 },
+{"sbsetw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBSETIW, MASK_SBSETIW, match_opcode, INSN_ALIAS },
+{"sbinvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBINVW, MASK_SBINVW, match_opcode, 0 },
+{"sbinvw", 64, INSN_CLASS_B_OR_ZBS, "d,s,<", MATCH_SBINVIW, MASK_SBINVIW, match_opcode, INSN_ALIAS },
+{"sbextw", 64, INSN_CLASS_B_OR_ZBS, "d,s,t", MATCH_SBEXTW, MASK_SBEXTW, match_opcode, 0 },
+
+{"cmix", 0, INSN_CLASS_ZBT, "d,t,s,r", MATCH_CMIX, MASK_CMIX, match_opcode, 0 },
+{"cmov", 0, INSN_CLASS_ZBT, "d,t,s,r", MATCH_CMOV, MASK_CMOV, match_opcode, 0 },
+{"fsri", 0, INSN_CLASS_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, 0 },
+{"fsl", 0, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSL, MASK_FSL, match_opcode, 0 },
+{"fsr", 0, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSR, MASK_FSR, match_opcode, 0 },
+{"fsr", 0, INSN_CLASS_ZBT, "d,s,r,>", MATCH_FSRI, MASK_FSRI, match_opcode, INSN_ALIAS },
+{"fsriw", 64, INSN_CLASS_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, 0 },
+{"fslw", 64, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSLW, MASK_FSLW, match_opcode, 0 },
+{"fsrw", 64, INSN_CLASS_ZBT, "d,s,r,t", MATCH_FSRW, MASK_FSRW, match_opcode, 0 },
+{"fsrw", 64, INSN_CLASS_ZBT, "d,s,r,<", MATCH_FSRIW, MASK_FSRIW, match_opcode, INSN_ALIAS },
+
+/* Bitmanip pseudo-instructions */
+{"rev.p", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev2.n", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev.n", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev4.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev2.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev8.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev4.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev2.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev16.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev8.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev4.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev2.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev32", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev16", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev8", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev4", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev2", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"rev", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+
+{"orc.p", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc2.n", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc.n", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc4.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc2.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc.b", 0, INSN_CLASS_B_OR_ZBB_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc8.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc4.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc2.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc16.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc8.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc4.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc2.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc32", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc16", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc8", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc4", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc2", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"orc", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+
+{"zip.n", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip2.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip4.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip2.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip8.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip4.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip2.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip16", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip8", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip4", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip2", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"zip", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+
+{"unzip.n", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip2.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip.b", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip4.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip2.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip.h", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip8.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip4.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip2.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip.w", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip16", 64, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip8", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip4", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip2", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+{"unzip", 0, INSN_CLASS_B_OR_ZBP, "d,s", 0, (int) M_PERM, match_never, INSN_MACRO },
+
/* Single-precision floating-point instruction subset */
{"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
{"frsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
@@ -926,12 +1129,25 @@ const struct riscv_ext_version riscv_ext_version_table[] =
{"c", ISA_SPEC_CLASS_20190608, 2, 0},
{"c", ISA_SPEC_CLASS_2P2, 2, 0},
+{"b", ISA_SPEC_CLASS_DRAFT, 0, 92},
+
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
+{"zba", ISA_SPEC_CLASS_DRAFT, 0, 92},
+{"zbb", ISA_SPEC_CLASS_DRAFT, 0, 92},
+{"zbc", ISA_SPEC_CLASS_DRAFT, 0, 92},
+{"zbe", ISA_SPEC_CLASS_DRAFT, 0, 92},
+{"zbf", ISA_SPEC_CLASS_DRAFT, 0, 92},
+{"zbm", ISA_SPEC_CLASS_DRAFT, 0, 92},
+{"zbp", ISA_SPEC_CLASS_DRAFT, 0, 92},
+{"zbr", ISA_SPEC_CLASS_DRAFT, 0, 92},
+{"zbs", ISA_SPEC_CLASS_DRAFT, 0, 92},
+{"zbt", ISA_SPEC_CLASS_DRAFT, 0, 92},
+
/* Terminate the list. */
{NULL, 0, 0, 0}
};
--
2.7.4
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