[Committed] IBM Z: Add risbgz and risbgnz extended mnemonics
Andreas Krebbel
krebbel@linux.ibm.com
Fri Dec 4 08:17:50 GMT 2020
These two extended mnemonics are documented in the Principles of
Operations manual but currently not supported by Binutils. They
provide aliases for already supported instructions with the zero flag
being set. The flag otherwise is mingled into one of the immediate
operands what makes asm code much harder to read.
No testsuite regressions on s390x.
opcodes/
* s390-opc.txt: Add risbgz and risbgnz.
* s390-opc.c (U6_26): New operand type.
(INSTR_RIE_RRUUU2, MASK_RIE_RRUUU2): New instruction format and
mask.
gas/
* testsuite/gas/s390/zarch-z10.s: Add tests for risbgz.
* testsuite/gas/s390/zarch-z10.d: Add regexp for risbgz.
* testsuite/gas/s390/zarch-zEC12.s: Add tests for risbgnz.
* testsuite/gas/s390/zarch-zEC12.d: Add regexp for risbgnz.
---
gas/ChangeLog | 7 +++++++
gas/testsuite/gas/s390/zarch-z10.d | 12 +++++++-----
gas/testsuite/gas/s390/zarch-z10.s | 4 +++-
gas/testsuite/gas/s390/zarch-zEC12.d | 20 +++++++++++---------
gas/testsuite/gas/s390/zarch-zEC12.s | 3 +++
opcodes/ChangeLog | 7 +++++++
opcodes/s390-opc.c | 28 ++++++++++++++++------------
opcodes/s390-opc.txt | 2 ++
8 files changed, 56 insertions(+), 27 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 96935a61f2c..c1310373ab1 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2020-12-04 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * testsuite/gas/s390/zarch-z10.s: Add tests for risbgz.
+ * testsuite/gas/s390/zarch-z10.d: Add regexp for risbgz.
+ * testsuite/gas/s390/zarch-zEC12.s: Add tests for risbgnz.
+ * testsuite/gas/s390/zarch-zEC12.d: Add regexp for risbgnz.
+
2020-12-03 Andreas Krebbel <krebbel@linux.ibm.com>
* testsuite/gas/s390/esa-g5.s: Test new extended mnemonics.
diff --git a/gas/testsuite/gas/s390/zarch-z10.d b/gas/testsuite/gas/s390/zarch-z10.d
index e60ec515547..183e98ee741 100644
--- a/gas/testsuite/gas/s390/zarch-z10.d
+++ b/gas/testsuite/gas/s390/zarch-z10.d
@@ -362,11 +362,13 @@ Disassembly of section .text:
.*: ec 67 d2 dc e6 54 [ ]*rnsbg %r6,%r7,210,220,230
.*: ec 67 d2 dc e6 57 [ ]*rxsbg %r6,%r7,210,220,230
.*: ec 67 d2 dc e6 56 [ ]*rosbg %r6,%r7,210,220,230
-.*: ec 67 d2 dc e6 55 [ ]*risbg %r6,%r7,210,220,230
-.*: c4 6f 00 00 00 00 [ ]*strl %r6,7f6 <foo\+0x7f6>
-.*: c4 6b 00 00 00 00 [ ]*stgrl %r6,7fc <foo\+0x7fc>
-.*: c4 67 00 00 00 00 [ ]*sthrl %r6,802 <foo\+0x802>
-.*: c6 60 00 00 00 00 [ ]*exrl %r6,808 <foo\+0x808>
+.*: ec 67 d2 14 e6 55 [ ]*risbg %r6,%r7,210,20,230
+.*: ec 67 d2 bc e6 55 [ ]*risbgz %r6,%r7,210,60,230
+.*: ec 67 d2 94 e6 55 [ ]*risbgz %r6,%r7,210,20,230
+.*: c4 6f 00 00 00 00 [ ]*strl %r6,802 <foo\+0x802>
+.*: c4 6b 00 00 00 00 [ ]*stgrl %r6,808 <foo\+0x808>
+.*: c4 67 00 00 00 00 [ ]*sthrl %r6,80e <foo\+0x80e>
+.*: c6 60 00 00 00 00 [ ]*exrl %r6,814 <foo\+0x814>
.*: af ee 6d 05 [ ]*mc 3333\(%r6\),238
.*: b9 a2 00 60 [ ]*ptf %r6
.*: b9 af 00 67 [ ]*pfmf %r6,%r7
diff --git a/gas/testsuite/gas/s390/zarch-z10.s b/gas/testsuite/gas/s390/zarch-z10.s
index bd292e998ad..5cfc533d4d1 100644
--- a/gas/testsuite/gas/s390/zarch-z10.s
+++ b/gas/testsuite/gas/s390/zarch-z10.s
@@ -356,7 +356,9 @@ foo:
rnsbg %r6,%r7,210,220,230
rxsbg %r6,%r7,210,220,230
rosbg %r6,%r7,210,220,230
- risbg %r6,%r7,210,220,230
+ risbg %r6,%r7,210,20,230
+ risbg %r6,%r7,210,188,230
+ risbgz %r6,%r7,210,20,230
strl %r6,.
stgrl %r6,.
sthrl %r6,.
diff --git a/gas/testsuite/gas/s390/zarch-zEC12.d b/gas/testsuite/gas/s390/zarch-zEC12.d
index a4be510d3a2..e25ac134e1f 100644
--- a/gas/testsuite/gas/s390/zarch-zEC12.d
+++ b/gas/testsuite/gas/s390/zarch-zEC12.d
@@ -47,6 +47,8 @@ Disassembly of section .text:
.*: eb 6c 7a 4d fe 2b [ ]*clgtnh %r6,-5555\(%r7\)
.*: eb 6c 7a 4d fe 2b [ ]*clgtnh %r6,-5555\(%r7\)
.*: ec 67 0c 0d 0e 59 [ ]*risbgn %r6,%r7,12,13,14
+.*: ec 67 0c bc 0e 59 [ ]*risbgnz %r6,%r7,12,60,14
+.*: ec 67 0c 94 0e 59 [ ]*risbgnz %r6,%r7,12,20,14
.*: ed 0f 8f a0 6d aa [ ]*cdzt %f6,4000\(16,%r8\),13
.*: ed 21 8f a0 4d ab [ ]*cxzt %f4,4000\(34,%r8\),13
.*: ed 0f 8f a0 6d a8 [ ]*czdt %f6,4000\(16,%r8\),13
@@ -54,16 +56,16 @@ Disassembly of section .text:
.*: b2 e8 c0 56 [ ]*ppa %r5,%r6,12
.*: b9 8f 60 59 [ ]*crdte %r5,%r6,%r9
.*: b9 8f 61 59 [ ]*crdte %r5,%r6,%r9,1
-.*: c5 a0 0c 00 00 0c [ ]*bprp 10,12a <bar>,12a <bar>
-.*: c5 a0 00 00 00 00 [ ]*bprp 10,118 <foo\+0x118>,118 <foo\+0x118>
-[ ]*119: R_390_PLT12DBL bar\+0x1
-[ ]*11b: R_390_PLT24DBL bar\+0x3
-.*: c7 a0 00 00 00 00 [ ]*bpp 10,11e <foo\+0x11e>,0
-[ ]*122: R_390_PLT16DBL bar\+0x4
-.*: c7 a0 00 00 00 00 [ ]*bpp 10,124 <foo\+0x124>,0
-[ ]*128: R_390_PC16DBL baz\+0x4
+.*: c5 a0 0c 00 00 0c [ ]*bprp 10,136 <bar>,136 <bar>
+.*: c5 a0 00 00 00 00 [ ]*bprp 10,124 <foo\+0x124>,124 <foo\+0x124>
+[ ]*125: R_390_PLT12DBL bar\+0x1
+[ ]*127: R_390_PLT24DBL bar\+0x3
+.*: c7 a0 00 00 00 00 [ ]*bpp 10,12a <foo\+0x12a>,0
+[ ]*12e: R_390_PLT16DBL bar\+0x4
+.*: c7 a0 00 00 00 00 [ ]*bpp 10,130 <foo\+0x130>,0
+[ ]*134: R_390_PC16DBL baz\+0x4
-000000000000012a <bar>:
+0000000000000136 <bar>:
.*: 07 07 [ ]*nopr %r7
diff --git a/gas/testsuite/gas/s390/zarch-zEC12.s b/gas/testsuite/gas/s390/zarch-zEC12.s
index 4754b2089c5..03b577e4830 100644
--- a/gas/testsuite/gas/s390/zarch-zEC12.s
+++ b/gas/testsuite/gas/s390/zarch-zEC12.s
@@ -44,6 +44,9 @@ foo:
clgtnh %r6,-5555(%r7)
risbgn %r6,%r7,12,13,14
+ risbgn %r6,%r7,12,188,14
+ risbgnz %r6,%r7,12,20,14
+
cdzt %f6,4000(16,%r8),13
cxzt %f4,4000(34,%r8),13
czdt %f6,4000(16,%r8),13
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c19c0aeba49..4ea3d76339e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2020-12-04 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * s390-opc.txt: Add risbgz and risbgnz.
+ * s390-opc.c (U6_26): New operand type.
+ (INSTR_RIE_RRUUU2, MASK_RIE_RRUUU2): New instruction format and
+ mask.
+
2020-12-03 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-opc.txt: Add extended mnemonics.
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 8505e9292b0..9804ebfca6d 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -218,32 +218,34 @@ const struct s390_operand s390_operands[] =
{ 8, 8, 0 },
#define U8_16 68 /* 8 bit unsigned value starting at 16 */
{ 8, 16, 0 },
-#define U8_24 69 /* 8 bit unsigned value starting at 24 */
+#define U6_26 69 /* 6 bit unsigned value starting at 26 */
+ { 6, 26, 0 },
+#define U8_24 70 /* 8 bit unsigned value starting at 24 */
{ 8, 24, 0 },
-#define U8_28 70 /* 8 bit unsigned value starting at 28 */
+#define U8_28 71 /* 8 bit unsigned value starting at 28 */
{ 8, 28, 0 },
-#define U8_32 71 /* 8 bit unsigned value starting at 32 */
+#define U8_32 72 /* 8 bit unsigned value starting at 32 */
{ 8, 32, 0 },
-#define U12_16 72 /* 12 bit unsigned value starting at 16 */
+#define U12_16 73 /* 12 bit unsigned value starting at 16 */
{ 12, 16, 0 },
-#define U16_16 73 /* 16 bit unsigned value starting at 16 */
+#define U16_16 74 /* 16 bit unsigned value starting at 16 */
{ 16, 16, 0 },
-#define U16_32 74 /* 16 bit unsigned value starting at 32 */
+#define U16_32 75 /* 16 bit unsigned value starting at 32 */
{ 16, 32, 0 },
-#define U32_16 75 /* 32 bit unsigned value starting at 16 */
+#define U32_16 76 /* 32 bit unsigned value starting at 16 */
{ 32, 16, 0 },
/* PC-relative address operands. */
-#define J12_12 76 /* 12 bit PC relative offset at 12 */
+#define J12_12 77 /* 12 bit PC relative offset at 12 */
{ 12, 12, S390_OPERAND_PCREL },
-#define J16_16 77 /* 16 bit PC relative offset at 16 */
+#define J16_16 78 /* 16 bit PC relative offset at 16 */
{ 16, 16, S390_OPERAND_PCREL },
-#define J16_32 78 /* 16 bit PC relative offset at 32 */
+#define J16_32 79 /* 16 bit PC relative offset at 32 */
{ 16, 32, S390_OPERAND_PCREL },
-#define J24_24 79 /* 24 bit PC relative offset at 24 */
+#define J24_24 80 /* 24 bit PC relative offset at 24 */
{ 24, 24, S390_OPERAND_PCREL },
-#define J32_16 80 /* 32 bit PC relative offset at 16 */
+#define J32_16 81 /* 32 bit PC relative offset at 16 */
{ 32, 16, S390_OPERAND_PCREL },
};
@@ -313,6 +315,7 @@ const struct s390_operand s390_operands[] =
#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */
#define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */
#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
+#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. rnsbg */
#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
@@ -534,6 +537,7 @@ const struct s390_operand s390_operands[] =
#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
#define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff }
#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index d84f9f798a4..2857ffbfbf9 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -970,6 +970,7 @@ ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch
ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch
ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch
ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch
+ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch
c40f strl RIL_RP "store relative long (32)" z10 zarch
c40b stgrl RIL_RP "store relative long (64)" z10 zarch
c407 sthrl RIL_RP "store halfword relative long" z10 zarch
@@ -1153,6 +1154,7 @@ eb0000000023 clt$12 RSY_R0RD "compare logical and trap 32 bit reg-mem" zEC12 zar
eb000000002b clgt RSY_RURD "compare logical and trap 64 bit reg-mem" zEC12 zarch
eb000000002b clgt$12 RSY_R0RD "compare logical and trap 64 bit reg-mem" zEC12 zarch
ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch
+ec0000800059 risbgnz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits nocc" zEC12 zarch
ed00000000aa cdzt RSL_LRDFU "convert from zoned long" zEC12 zarch
ed00000000ab cxzt RSL_LRDFEU "convert from zoned extended" zEC12 zarch
ed00000000a8 czdt RSL_LRDFU "convert to zoned long" zEC12 zarch
--
2.28.0
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