[0/8] RISC-V: Architecture string improvement

[Nelson Chu]

On Tue, Dec 1, 2020 at 8:05 AM Jim Wilson <jimw@sifive.com> wrote:
> I noticed a comment typo in part 7, Negaive->Negative

OK I will fix the typo.

> Part 6 adds a rule for zicsr
>     * Add zicsr only when the i's version less then 2.1.
> I think zifencei should be handled the same, for this rule only, as it was added at the same time.

Make sense, this is better.

> Otherwise this looks OK to me with those two minor fixes.

Thanks, I will commit these patches when I have fixed these two fixs.

> zifencei doesn't control the fence.i instruction in riscv-opc.c but then we have the same problem with zicsr which doesn't control the csr* instructions.  This can be fixed later.

Noted, this will be fixed in the future patches.

> There is a testcase for rv32ef which says "rv32e does not support the 'f' extension" which isn't quite right.  For ISA v2.2 (e v1.9), rv32ef is not allowed.  However, that rule was changed at some later point, and rv32ef is now allowed.  Looks like this happened in ISA version 20190608 (still e v1.9).  But we have the problem that the toolchain doesn't support this yet as the ABI is broken and no one has demanded support for it yet.  So the error should really depend on the ISA version, and for ISA v2.2 we should say that rv32e doesn't support f, and for later ISA versions we should say that the toolchain doesn't support rv32e with f yet.  This can be fixed later.  Or maybe we don't fix it as I don't think that anyone cares.  Not until we get the new EABI and then can implement rv32ef properly.

Thanks for mentioning these in detail.  I will fix the zifencei and
zicsr in the riscv-opc.c first, and then we can decide whether the
rv32ef should be fixed next.

Thanks
Nelson