[PATCH 1/1] CSKY: Add new arch CK860.
Cooper Qu
cooper.qu@linux.alibaba.com
Mon Aug 24 12:13:47 GMT 2020
bfd/
* bfd-in2.h (bfd_mach_ck860): New.
* cpu-csky.c (arch_info_struct): Add item for CK860.
gas/
* config/tc-csky.c (csky_archs): Add item for CK860,
change ck810 and ck807's arch_flag.
(csky_cpus): Add item for CK860.
(md_begin): Enable DSP for CK810 and CK807 by default.
(md_apply_fix): Fix CKCORE_TLS_IE32 relocation failure.
* gas/testsuite/gas/csky/cskyv2_all.d: Change 'sync 0'
to 'sync'.
* gas/testsuite/gas/csky/cskyv2_all.s: Likewise.
* gas/testsuite/gas/csky/cskyv2_ck860.d: New.
* gas/testsuite/gas/csky/cskyv2_ck860.s: New.
* gas/testsuite/gas/csky/enhance_dsp.d: Change plsli.u16
to plsli.16.
* gas/testsuite/gas/csky/enhance_dsp.s: Likewise.
include/
* opcode/csky.h (CSKYV2_ISA_10E60): New.
(CSKY_ARCH_860): New.
opcode/
* csky-dis.c (csky_find_inst_info): Skip CK860's instructions
in other CPUs to speed up disassembling.
* csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
Change plsli.u16 to plsli.16, change sync's operand format.
Change-Id: I80ec1a9c0cc600d668082a9b91ae6d45b33ec0fc
---
bfd/ChangeLog | 5 ++
bfd/bfd-in2.h | 1 +
bfd/cpu-csky.c | 1 +
gas/ChangeLog | 16 ++++
gas/config/tc-csky.c | 26 ++++--
gas/testsuite/gas/csky/cskyv2_all.d | 2 +-
gas/testsuite/gas/csky/cskyv2_all.s | 2 +-
gas/testsuite/gas/csky/cskyv2_ck860.d | 41 +++++++++
gas/testsuite/gas/csky/cskyv2_ck860.s | 35 ++++++++
gas/testsuite/gas/csky/enhance_dsp.d | 2 +-
gas/testsuite/gas/csky/enhance_dsp.s | 2 +-
include/ChangeLog | 5 ++
include/opcode/csky.h | 2 +
opcodes/ChangeLog | 7 ++
opcodes/csky-dis.c | 9 ++
opcodes/csky-opc.h | 118 ++++++++++++++++++++++++--
16 files changed, 259 insertions(+), 15 deletions(-)
create mode 100644 gas/testsuite/gas/csky/cskyv2_ck860.d
create mode 100644 gas/testsuite/gas/csky/cskyv2_ck860.s
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index eb4d882ce97..17a5a82d0dc 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,8 @@
+2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * bfd-in2.h (bfd_mach_ck860): New.
+ * cpu-csky.c (arch_info_struct): Add item for CK860.
+
2020-08-23 John David Anglin <danglin@gcc.gnu.org>
PR binutils/26357
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 94d3195836a..a16d03780e2 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1952,6 +1952,7 @@ enum bfd_architecture
#define bfd_mach_ck803 5
#define bfd_mach_ck807 6
#define bfd_mach_ck810 7
+#define bfd_mach_ck860 8
bfd_arch_last
};
diff --git a/bfd/cpu-csky.c b/bfd/cpu-csky.c
index cd537278f04..4ec6db62984 100644
--- a/bfd/cpu-csky.c
+++ b/bfd/cpu-csky.c
@@ -53,6 +53,7 @@ static const bfd_arch_info_type arch_info_struct[] =
N (bfd_mach_ck803, "csky:ck803", FALSE, & arch_info_struct[5]),
N (bfd_mach_ck807, "csky:ck807", FALSE, & arch_info_struct[6]),
N (bfd_mach_ck810, "csky:ck810", FALSE, & arch_info_struct[7]),
+ N (bfd_mach_ck860, "csky:ck860", FALSE, & arch_info_struct[8]),
N (bfd_mach_ck_unknown, "csky:any", FALSE, NULL)
};
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6b634a0f360..98733ae0ef7 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,19 @@
+2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (csky_archs): Add item for CK860,
+ change ck810 and ck807's arch_flag.
+ (csky_cpus): Add item for CK860.
+ (md_begin): Enable DSP for CK810 and CK807 by default.
+ (md_apply_fix): Fix CKCORE_TLS_IE32 relocation failure.
+ * gas/testsuite/gas/csky/cskyv2_all.d: Change 'sync 0'
+ to 'sync'.
+ * gas/testsuite/gas/csky/cskyv2_all.s: Likewise.
+ * gas/testsuite/gas/csky/cskyv2_ck860.d: New.
+ * gas/testsuite/gas/csky/cskyv2_ck860.s: New.
+ * gas/testsuite/gas/csky/enhance_dsp.d: Change plsli.u16
+ to plsli.16.
+ * gas/testsuite/gas/csky/enhance_dsp.s: Likewise.
+
2020-08-24 Alan Modra <amodra@gmail.com>
* config/tc-aarch64.c (md_begin): Don't bother checking for
diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c
index d16c448f050..f621fa9824b 100644
--- a/gas/config/tc-csky.c
+++ b/gas/config/tc-csky.c
@@ -564,13 +564,15 @@ const struct csky_arch_info csky_archs[] =
{"ck801", CSKY_ARCH_801, bfd_mach_ck801},
{"ck802", CSKY_ARCH_802, bfd_mach_ck802},
{"ck803", CSKY_ARCH_803, bfd_mach_ck803},
-#define CSKY_ARCH_807_BASE CSKY_ARCH_807 | CSKY_ARCH_DSP
-#define CSKY_ARCH_810_BASE CSKY_ARCH_810 | CSKY_ARCH_DSP
- {"ck807", CSKY_ARCH_807_BASE, bfd_mach_ck807},
- {"ck810", CSKY_ARCH_810_BASE, bfd_mach_ck810},
+ {"ck807", CSKY_ARCH_807, bfd_mach_ck807},
+ {"ck810", CSKY_ARCH_810, bfd_mach_ck810},
+ {"ck860", CSKY_ARCH_860, bfd_mach_ck860},
{NULL, 0, 0}
};
+#define CSKY_ARCH_807_BASE CSKY_ARCH_807 | CSKY_ARCH_DSP
+#define CSKY_ARCH_810_BASE CSKY_ARCH_810 | CSKY_ARCH_DSP
+
/* C-SKY cpus table. */
const struct csky_cpu_info csky_cpus[] =
{
@@ -683,6 +685,11 @@ const struct csky_cpu_info csky_cpus[] =
{"ck810ft", CSKY_ARCH_810_BASE | CSKY_ARCH_FLOAT, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_VDSP | CSKY_ISA_FLOAT_810 | CSKY_ISA_TRUST},
{"ck810ftv", CSKY_ARCH_810_BASE | CSKY_ARCH_FLOAT, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_VDSP | CSKY_ISA_FLOAT_810 | CSKY_ISA_TRUST},
+ /* CK860 Series. */
+#define CSKY_ISA_860 (CSKY_ISA_810 | CSKYV2_ISA_10E60)
+#define CSKY_ISA_FLOAT_860 (CSKY_ISA_FLOAT_810)
+ {"ck860", CSKY_ARCH_860, CSKY_ISA_860},
+
{NULL, 0, 0}
};
@@ -1207,7 +1214,14 @@ md_begin (void)
as_warn (_("-mcpu conflict with other model parameters, using -mcpu"));
}
else if (arch_flag != 0)
- mach_flag |= arch_flag | flags;
+ {
+ if ((arch_flag & CSKY_ARCH_MASK) == CSKY_ARCH_810
+ || ((arch_flag & CSKY_ARCH_MASK) == CSKY_ARCH_807)) {
+ /* CK807 and CK810 have DSP instruction by default. */
+ mach_flag |= CSKY_ARCH_DSP;
+ }
+ mach_flag |= arch_flag | flags;
+ }
else
{
#ifdef TARGET_WITH_CPU
@@ -4941,6 +4955,7 @@ md_apply_fix (fixS *fixP,
struct tls_addend *ta = &(fixP->tc_fix_data);
fixP->fx_offset = (fixP->fx_frag->fr_address + fixP->fx_where
- (ta->frag->fr_address + ta->offset));
+ *valP = fixP->fx_offset;
}
/* Fall through. */
case BFD_RELOC_CKCORE_TLS_LE32:
@@ -5002,6 +5017,7 @@ md_apply_fix (fixS *fixP,
struct tls_addend *ta = &(fixP->tc_fix_data);
fixP->fx_offset = (fixP->fx_frag->fr_address + fixP->fx_where
- (ta->frag->fr_address + ta->offset));
+ *valP = fixP->fx_offset;
}
/* Fall through. */
case BFD_RELOC_CKCORE_TLS_LE32:
diff --git a/gas/testsuite/gas/csky/cskyv2_all.d b/gas/testsuite/gas/csky/cskyv2_all.d
index b17a5e74f57..5092690aa3f 100644
--- a/gas/testsuite/gas/csky/cskyv2_all.d
+++ b/gas/testsuite/gas/csky/cskyv2_all.d
@@ -163,7 +163,7 @@ Disassembly of section \.text:
\s*[0-9a-f]*:\s*c4139c40\s*mthi\s*r19
\s*[0-9a-f]*:\s*c4009c83\s*mflo\s*r3
\s*[0-9a-f]*:\s*c4089d00\s*mtlo\s*r8
-\s*[0-9a-f]*:\s*c0000420\s*sync\s*0
+\s*[0-9a-f]*:\s*c0000420\s*sync
\s*[0-9a-f]*:\s*c0200420\s*sync\s*1
\s*[0-9a-f]*:\s*c2800420\s*sync\s*20
\s*[0-9a-f]*:\s*c0601c20\s*idly\s*4
diff --git a/gas/testsuite/gas/csky/cskyv2_all.s b/gas/testsuite/gas/csky/cskyv2_all.s
index 3826b0602c8..6e6902e077b 100644
--- a/gas/testsuite/gas/csky/cskyv2_all.s
+++ b/gas/testsuite/gas/csky/cskyv2_all.s
@@ -157,7 +157,7 @@ all:
mthi r19
mflo r3
mtlo r8
- sync 0
+ sync
sync 1
sync 20
idly 0
diff --git a/gas/testsuite/gas/csky/cskyv2_ck860.d b/gas/testsuite/gas/csky/cskyv2_ck860.d
new file mode 100644
index 00000000000..2beb8845b7b
--- /dev/null
+++ b/gas/testsuite/gas/csky/cskyv2_ck860.d
@@ -0,0 +1,41 @@
+# name: csky - ck860
+#as: -mcpu=ck860
+#objdump: -D
+
+.*: +file format .*csky.*
+
+Disassembly of section \.text:
+#...
+\s*[0-9a-f]*:\s*c0008820\s*tlbi.all
+\s*[0-9a-f]*:\s*c2008820\s*tlbi.alls
+\s*[0-9a-f]*:\s*c0618820\s*tlbi.va\s*r1
+\s*[0-9a-f]*:\s*c26f8820\s*tlbi.vas\s*r15
+\s*[0-9a-f]*:\s*c0218820\s*tlbi.asid\s*r1
+\s*[0-9a-f]*:\s*c22f8820\s*tlbi.asids\s*r15
+\s*[0-9a-f]*:\s*c04f8820\s*tlbi.vaa\s*r15
+\s*[0-9a-f]*:\s*c24f8820\s*tlbi.vaas\s*r15
+\s*[0-9a-f]*:\s*c1df9420\s*dcache.cisw\s*r31
+\s*[0-9a-f]*:\s*c1ff9420\s*dcache.civa\s*r31
+\s*[0-9a-f]*:\s*c1809420\s*dcache.ciall
+\s*[0-9a-f]*:\s*c0df9420\s*dcache.csw\s*r31
+\s*[0-9a-f]*:\s*c0ff9420\s*dcache.cva\s*r31
+\s*[0-9a-f]*:\s*c2ff9420\s*dcache.cval1\s*r31
+\s*[0-9a-f]*:\s*c0809420\s*dcache.call
+\s*[0-9a-f]*:\s*c15f9420\s*dcache.isw\s*r31
+\s*[0-9a-f]*:\s*c17f9420\s*dcache.iva\s*r31
+\s*[0-9a-f]*:\s*c1009420\s*dcache.iall
+\s*[0-9a-f]*:\s*c1009020\s*icache.iall
+\s*[0-9a-f]*:\s*c3009020\s*icache.ialls
+\s*[0-9a-f]*:\s*c0bf9020\s*icache.iva\s*r31
+\s*[0-9a-f]*:\s*c000842f\s*bar.brwarw
+\s*[0-9a-f]*:\s*c200842f\s*bar.brwarws
+\s*[0-9a-f]*:\s*c0008425\s*bar.brar
+\s*[0-9a-f]*:\s*c2008425\s*bar.brars
+\s*[0-9a-f]*:\s*c000842a\s*bar.bwaw
+\s*[0-9a-f]*:\s*c200842a\s*bar.bwaws
+\s*[0-9a-f]*:\s*c2200420\s*sync.is
+\s*[0-9a-f]*:\s*c0200420\s*sync.i
+\s*[0-9a-f]*:\s*c2000420\s*sync.s
+\s*[0-9a-f]*:\s*c0000420\s*sync
+\s*[0-9a-f]*:\s*d8437000\s*ldex.w\s*r2,\s*\(r3,\s*0x0\)
+\s*[0-9a-f]*:\s*dc437000\s*stex.w\s*r2,\s*\(r3,\s*0x0\)
\ No newline at end of file
diff --git a/gas/testsuite/gas/csky/cskyv2_ck860.s b/gas/testsuite/gas/csky/cskyv2_ck860.s
new file mode 100644
index 00000000000..632b43319f6
--- /dev/null
+++ b/gas/testsuite/gas/csky/cskyv2_ck860.s
@@ -0,0 +1,35 @@
+ck860:
+ tlbi.all
+ tlbi.alls
+ tlbi.va r1
+ tlbi.vas r15
+ tlbi.asid r1
+ tlbi.asids r15
+ tlbi.vaa r15
+ tlbi.vaas r15
+ dcache.cisw r31
+ dcache.civa r31
+ dcache.ciall
+ dcache.csw r31
+ dcache.cva r31
+ dcache.cval1 r31
+ dcache.call
+ dcache.isw r31
+ dcache.iva r31
+ dcache.iall
+ icache.iall
+ icache.ialls
+ icache.iva r31
+ bar.brwarw
+ bar.brwarws
+ bar.brar
+ bar.brars
+ bar.bwaw
+ bar.bwaws
+ sync.is
+ sync.i
+ sync.s
+ sync
+
+ ldex.w r2, (r3, 0)
+ stex.w r2, (r3, 0)
diff --git a/gas/testsuite/gas/csky/enhance_dsp.d b/gas/testsuite/gas/csky/enhance_dsp.d
index eaf91259f8b..96d26ab6c50 100644
--- a/gas/testsuite/gas/csky/enhance_dsp.d
+++ b/gas/testsuite/gas/csky/enhance_dsp.d
@@ -109,7 +109,7 @@ Disassembly of section \.text:
\s*[0-9a-f]*:\s*f883d242\s*plsr\.u16\s*r2,\s*r3,\s*r4
\s*[0-9a-f]*:\s*f8e3d302\s*plsri\.u16\.r\s*r2,\s*r3,\s*8
\s*[0-9a-f]*:\s*f883d342\s*plsr\.u16\.r\s*r2,\s*r3,\s*r4
-\s*[0-9a-f]*:\s*f8e3d402\s*plsli\.u16\s*r2,\s*r3,\s*8
+\s*[0-9a-f]*:\s*f8e3d402\s*plsli\.16\s*r2,\s*r3,\s*8
\s*[0-9a-f]*:\s*fa03d442\s*plsl\.u16\s*r2,\s*r3,\s*r16
\s*[0-9a-f]*:\s*f8e3d502\s*plsli\.u16\.s\s*r2,\s*r3,\s*8
\s*[0-9a-f]*:\s*f8e3d582\s*plsli\.s16\.s\s*r2,\s*r3,\s*8
diff --git a/gas/testsuite/gas/csky/enhance_dsp.s b/gas/testsuite/gas/csky/enhance_dsp.s
index 755235dab3a..32772e27097 100644
--- a/gas/testsuite/gas/csky/enhance_dsp.s
+++ b/gas/testsuite/gas/csky/enhance_dsp.s
@@ -109,7 +109,7 @@ hello:
plsr.u16 r2, r3, r4
plsri.u16.r r2, r3, 8
plsr.u16.r r2, r3, r4
- plsli.u16 r2, r3, 8
+ plsli.16 r2, r3, 8
plsl.u16 r2, r3, r16
plsli.u16.s r2, r3, 8
plsli.s16.s r2, r3, 8
diff --git a/include/ChangeLog b/include/ChangeLog
index 22bf5a4c041..2ec02dc5000 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * opcode/csky.h (CSKYV2_ISA_10E60): New.
+ (CSKY_ARCH_860): New.
+
2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
* csky.h (CSKYV2_ISA_3E3R2): New.
diff --git a/include/opcode/csky.h b/include/opcode/csky.h
index 9b9dcc3289e..098bdc9ba65 100644
--- a/include/opcode/csky.h
+++ b/include/opcode/csky.h
@@ -30,6 +30,7 @@
#define CSKYV2_ISA_7E10 (1 << 5)
#define CSKYV2_ISA_3E3R1 (1 << 6)
#define CSKYV2_ISA_3E3R2 (1 << 7)
+#define CSKYV2_ISA_10E60 (1 << 8)
#define CSKY_ISA_TRUST (1 << 11)
#define CSKY_ISA_CACHE (1 << 12)
@@ -70,6 +71,7 @@
#define CSKY_ARCH_803 0x9
#define CSKY_ARCH_807 0x6
#define CSKY_ARCH_810 0x8
+#define CSKY_ARCH_860 0xb
#define CSKY_ARCH_MAC (1 << 15)
#define CSKY_ARCH_DSP (1 << 14)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index effcd63845f..f2dbc22e806 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
+ in other CPUs to speed up disassembling.
+ * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
+ Change plsli.u16 to plsli.16, change sync's operand format.
+
2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
* csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
diff --git a/opcodes/csky-dis.c b/opcodes/csky-dis.c
index bc6820ae076..537725baa40 100644
--- a/opcodes/csky-dis.c
+++ b/opcodes/csky-dis.c
@@ -159,6 +159,15 @@ csky_find_inst_info (struct csky_opcode_info const **pinfo,
p = g_opcodeP;
while (p->mnemonic)
{
+ /* FIXME: Skip 860's instruction in other CPUs. It is not suitable.
+ These codes need to be optimized. */
+ if (((CSKY_ARCH_MASK & mach_flag) != CSKY_ARCH_860)
+ && (p->isa_flag32 & CSKYV2_ISA_10E60))
+ {
+ p++;
+ continue;
+ }
+
/* Get the opcode mask. */
for (i = 0; i < OP_TABLE_NUM; i++)
if (length == 2)
diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h
index 30894033367..796d3757024 100644
--- a/opcodes/csky-opc.h
+++ b/opcodes/csky-opc.h
@@ -3401,11 +3401,6 @@ const struct csky_opcode csky_v2_opcodes[] =
(0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT),
(16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
CSKY_ISA_FLOAT_1E2),
- DOP32 ("sync",
- OPCODE_INFO1 (0xc0000420,
- (21_25, IMM5b, OPRND_SHIFT_0_BIT)),
- OPCODE_INFO0 (0xc0000420),
- CSKYV2_ISA_E1),
DOP32 ("idly",
OPCODE_INFO1 (0xc0001c20,
(21_25, OIMM5b_IDLY, OPRND_SHIFT_0_BIT)),
@@ -4681,6 +4676,117 @@ const struct csky_opcode csky_v2_opcodes[] =
#undef _RELAX
#define _RELAX 0
+ /* CK860 instructions. */
+ OP32("sync.is",
+ OPCODE_INFO0(0xc2200420),
+ CSKYV2_ISA_10E60),
+ OP32("sync.i",
+ OPCODE_INFO0(0xc0200420),
+ CSKYV2_ISA_10E60),
+ OP32("sync.s",
+ OPCODE_INFO0(0xc2000420),
+ CSKYV2_ISA_10E60),
+ OP32("bar.brwarw",
+ OPCODE_INFO0(0xc000842f),
+ CSKYV2_ISA_10E60),
+ OP32("bar.brwarws",
+ OPCODE_INFO0(0xc200842f),
+ CSKYV2_ISA_10E60),
+ OP32("bar.brar",
+ OPCODE_INFO0(0xc0008425),
+ CSKYV2_ISA_10E60),
+ OP32("bar.brars",
+ OPCODE_INFO0(0xc2008425),
+ CSKYV2_ISA_10E60),
+ OP32("bar.bwaw",
+ OPCODE_INFO0(0xc000842a),
+ CSKYV2_ISA_10E60),
+ OP32("bar.bwaws",
+ OPCODE_INFO0(0xc200842a),
+ CSKYV2_ISA_10E60),
+ OP32("icache.iall",
+ OPCODE_INFO0(0xc1009020),
+ CSKYV2_ISA_10E60),
+ OP32("icache.ialls",
+ OPCODE_INFO0(0xc3009020),
+ CSKYV2_ISA_10E60),
+ OP32("icache.iva",
+ OPCODE_INFO1(0xc0a09020,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("dcache.iall",
+ OPCODE_INFO0(0xc1009420),
+ CSKYV2_ISA_10E60),
+ OP32("dcache.iva",
+ OPCODE_INFO1(0xc1609420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("dcache.isw",
+ OPCODE_INFO1(0xc1409420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("dcache.call",
+ OPCODE_INFO0(0xc0809420),
+ CSKYV2_ISA_10E60),
+ OP32("dcache.cva",
+ OPCODE_INFO1(0xc0e09420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("dcache.cval1",
+ OPCODE_INFO1(0xc2e09420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("dcache.csw",
+ OPCODE_INFO1(0xc0c09420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("dcache.ciall",
+ OPCODE_INFO0(0xc1809420),
+ CSKYV2_ISA_10E60),
+ OP32("dcache.civa",
+ OPCODE_INFO1(0xc1e09420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("dcache.cisw",
+ OPCODE_INFO1(0xc1c09420,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("tlbi.vaa",
+ OPCODE_INFO1(0xc0408820,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("tlbi.vaas",
+ OPCODE_INFO1(0xc2408820,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("tlbi.asid",
+ OPCODE_INFO1(0xc0208820,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("tlbi.asids",
+ OPCODE_INFO1(0xc2208820,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("tlbi.va",
+ OPCODE_INFO1(0xc0608820,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("tlbi.vas",
+ OPCODE_INFO1(0xc2608820,
+ (16_20, AREG, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_10E60),
+ OP32("tlbi.all",
+ OPCODE_INFO0(0xc0008820),
+ CSKYV2_ISA_10E60),
+ OP32("tlbi.alls",
+ OPCODE_INFO0(0xc2008820),
+ CSKYV2_ISA_10E60),
+ DOP32("sync",
+ OPCODE_INFO0(0xc0000420),
+ OPCODE_INFO1(0xc0000420,
+ (21_25, IMM5b, OPRND_SHIFT_0_BIT)),
+ CSKYV2_ISA_E1),
+
/* The followings are enhance DSP instructions. */
DOP32_WITH_WORK ("bloop",
OPCODE_INFO3 (0xe9c00000,
@@ -5325,7 +5431,7 @@ const struct csky_opcode csky_v2_opcodes[] =
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP_ENHANCE),
- OP32 ("plsli.u16",
+ OP32 ("plsli.16",
OPCODE_INFO3 (0xf800d400,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
--
2.26.2
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