[PATCH] CSKY: Add ck803r2 series cpu.
Lifang Xia
lifang_xia@c-sky.com
Mon Aug 24 02:28:35 GMT 2020
Merged.
On 2020/8/21 18:08, Cooper Qu wrote:
> gas/
> * config/tc-csky.c (CSKY_ISA_803R2): New.
> (csky_archs): Add ck803r2 series.
> (md_begin): Fix warning about -medsp.
> (csky_get_freg_val): Support lowercase of fpu register name.
> * testsuite/gas/csky/cskyv2_ck803r2.s: New file.
> * testsuite/gas/csky/cskyv2_ck803r2.d: New file.
>
> include/
> * csky.h (CSKYV2_ISA_3E3R2): New.
>
> opcodes/
> * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
>
> ---
> gas/ChangeLog | 9 +++++
> gas/config/tc-csky.c | 52 +++++++++++++++++++++----
> gas/testsuite/gas/csky/cskyv2_ck803r2.d | 12 ++++++
> gas/testsuite/gas/csky/cskyv2_ck803r2.s | 6 +++
> include/ChangeLog | 4 ++
> include/opcode/csky.h | 1 +
> opcodes/ChangeLog | 4 ++
> opcodes/csky-opc.h | 11 +++++-
> 8 files changed, 89 insertions(+), 10 deletions(-)
> create mode 100644 gas/testsuite/gas/csky/cskyv2_ck803r2.d
> create mode 100644 gas/testsuite/gas/csky/cskyv2_ck803r2.s
>
> diff --git a/gas/ChangeLog b/gas/ChangeLog
> index 94ad709568f..2ca9cc308e8 100644
> --- a/gas/ChangeLog
> +++ b/gas/ChangeLog
> @@ -1,3 +1,12 @@
> +2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
> +
> + * config/tc-csky.c (CSKY_ISA_803R2): New.
> + (csky_archs): Add ck803r2 series.
> + (md_begin): Fix warning about -medsp.
> + (csky_get_freg_val): Support lowercase of fpu register name.
> + * testsuite/gas/csky/cskyv2_ck803r2.s: New file.
> + * testsuite/gas/csky/cskyv2_ck803r2.d: New file.
> +
> 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
>
> * config/tc-csky.c (csky_insn_info): Add member last_isize.
> diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c
> index 49a52d442a0..29f017c80f7 100644
> --- a/gas/config/tc-csky.c
> +++ b/gas/config/tc-csky.c
> @@ -604,6 +604,7 @@ const struct csky_cpu_info csky_cpus[] =
> /* CK803 series. */
> #define CSKY_ISA_803 (CSKY_ISA_802 | CSKYV2_ISA_2E3 | CSKY_ISA_MP)
> #define CSKY_ISA_803R1 (CSKY_ISA_803 | CSKYV2_ISA_3E3R1)
> +#define CSKY_ISA_803R2 (CSKY_ISA_803 | CSKYV2_ISA_3E3R1 | CSKYV2_ISA_3E3R2)
> #define CSKY_ISA_FLOAT_803 (CSKY_ISA_FLOAT_E1 | CSKY_ISA_FLOAT_1E3)
> {"ck803", CSKY_ARCH_803, CSKY_ISA_803 },
> {"ck803h", CSKY_ARCH_803, CSKY_ISA_803 },
> @@ -636,6 +637,22 @@ const struct csky_cpu_info csky_cpus[] =
> {"ck803eftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
> {"ck803ehftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
>
> + {"ck803r2", CSKY_ARCH_803, CSKY_ISA_803R2},
> + {"ck803hr2", CSKY_ARCH_803, CSKY_ISA_803R2},
> + {"ck803tr2", CSKY_ARCH_803, CSKY_ISA_803R2 | CSKY_ISA_TRUST},
> + {"ck803htr2", CSKY_ARCH_803, CSKY_ISA_803R2 | CSKY_ISA_TRUST},
> + {"ck803fr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803},
> + {"ck803fhr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803},
> + {"ck803er2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE},
> + {"ck803ehr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE},
> + {"ck803etr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
> + {"ck803ehtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
> + {"ck803efr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
> + {"ck803efhr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
> + {"ck803ftr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
> + {"ck803eftr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
> + {"ck803efhtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
> +
> {"ck803s", CSKY_ARCH_803, CSKY_ISA_803R1 },
> {"ck803se", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKYV2_ISA_DSP},
> {"ck803sj", CSKY_ARCH_803 | CSKY_ARCH_JAVA, CSKY_ISA_803R1 | CSKY_ISA_JAVA},
> @@ -1250,16 +1267,34 @@ md_begin (void)
> {
> if (IS_CSKY_ARCH_803 (mach_flag))
> {
> - /* In 803, dspv1 is conflict with dspv2. We keep dspv2. */
> - if ((dsp_flag & CSKY_DSP_FLAG_V1) && (dsp_flag & CSKY_DSP_FLAG_V2))
> - as_warn (_("option -mdsp conflicts with -medsp, only enabling -medsp"));
> - isa_flag &= ~(CSKY_ISA_MAC_DSP | CSKY_ISA_DSP);
> - isa_flag |= CSKY_ISA_DSP_ENHANCE;
> + if ((dsp_flag & CSKY_DSP_FLAG_V1))
> + {
> + isa_flag |= (CSKY_ISA_MAC_DSP | CSKY_ISA_DSP);
> + isa_flag &= ~CSKY_ISA_DSP_ENHANCE;
> + }
> +
> + if ((dsp_flag & CSKY_DSP_FLAG_V2))
> + {
> + isa_flag &= ~(CSKY_ISA_MAC_DSP | CSKY_ISA_DSP);
> + isa_flag |= CSKY_ISA_DSP_ENHANCE;
> + }
> +
> + if ((dsp_flag & CSKY_DSP_FLAG_V1)
> + && (dsp_flag & CSKY_DSP_FLAG_V2))
> + {
> + /* In 803, dspv1 is conflict with dspv2. We keep dspv2. */
> + as_warn ("option -mdsp conflicts with -medsp, only enabling -medsp");
> + isa_flag &= ~(CSKY_ISA_MAC_DSP | CSKY_ISA_DSP);
> + isa_flag |= CSKY_ISA_DSP_ENHANCE;
> + }
> }
> else
> {
> - isa_flag &= ~CSKY_ISA_DSP_ENHANCE;
> - as_warn (_("-medsp option is only supported by ck803s, ignoring -medsp"));
> + if (dsp_flag & CSKY_DSP_FLAG_V2)
> + {
> + isa_flag &= ~CSKY_ISA_DSP_ENHANCE;
> + as_warn ("-medsp option is only supported by ck803s, ignoring -medsp");
> + }
> }
> ;
> }
> @@ -2331,7 +2366,8 @@ csky_get_freg_val (char *str, int *len)
> {
> int reg = 0;
> char *s = NULL;
> - if ((str[0] == 'v' || str[0] == 'f') && (str[1] == 'r'))
> + if ((TOLOWER(str[0]) == 'v' || TOLOWER(str[0]) == 'f')
> + && (TOLOWER(str[1]) == 'r'))
> {
> /* It is fpu register. */
> s = &str[2];
> diff --git a/gas/testsuite/gas/csky/cskyv2_ck803r2.d b/gas/testsuite/gas/csky/cskyv2_ck803r2.d
> new file mode 100644
> index 00000000000..298022aefdb
> --- /dev/null
> +++ b/gas/testsuite/gas/csky/cskyv2_ck803r2.d
> @@ -0,0 +1,12 @@
> +# name: csky - ck803r2
> +#as: -mcpu=ck803r2
> +#objdump: -D
> +
> +.*: +file format .*csky.*
> +
> +Disassembly of section \.text:
> +#...
> +\s*[0-9a-f]*:\s*e8200002\s*bnezad\s*r0, 0x4.*
> +#...
> +\s*[0-9a-f]*:\s*6c03\s*mov\s*r0,\s*r0
> +\s*[0-9a-f]*:\s*e820fffd\s*bnezad\s*r0,\s*0.*
> diff --git a/gas/testsuite/gas/csky/cskyv2_ck803r2.s b/gas/testsuite/gas/csky/cskyv2_ck803r2.s
> new file mode 100644
> index 00000000000..4c9e923e98e
> --- /dev/null
> +++ b/gas/testsuite/gas/csky/cskyv2_ck803r2.s
> @@ -0,0 +1,6 @@
> +ck803r2:
> + bnezad r0, hello
> +
> +hello:
> + nop
> + bnezad r0, ck803r2
> diff --git a/include/ChangeLog b/include/ChangeLog
> index d0475de1ce9..62e14b7472f 100644
> --- a/include/ChangeLog
> +++ b/include/ChangeLog
> @@ -1,3 +1,7 @@
> +2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
> +
> + * csky.h (CSKYV2_ISA_3E3R2): New.
> +
> 2020-08-10 Alex Coplan <alex.coplan@arm.com>
>
> * opcode/aarch64.h (AARCH64_MAX_SYSREG_NAME_LEN): New.
> diff --git a/include/opcode/csky.h b/include/opcode/csky.h
> index aa6bcce3d27..9b9dcc3289e 100644
> --- a/include/opcode/csky.h
> +++ b/include/opcode/csky.h
> @@ -29,6 +29,7 @@
> #define CSKYV2_ISA_3E7 (1 << 4)
> #define CSKYV2_ISA_7E10 (1 << 5)
> #define CSKYV2_ISA_3E3R1 (1 << 6)
> +#define CSKYV2_ISA_3E3R2 (1 << 7)
>
> #define CSKY_ISA_TRUST (1 << 11)
> #define CSKY_ISA_CACHE (1 << 12)
> diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
> index 6578fbf37f0..b65e701c878 100644
> --- a/opcodes/ChangeLog
> +++ b/opcodes/ChangeLog
> @@ -1,3 +1,7 @@
> +2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
> +
> + * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
> +
> 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
>
> * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
> diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h
> index 6dcf742e482..30894033367 100644
> --- a/opcodes/csky-opc.h
> +++ b/opcodes/csky-opc.h
> @@ -4565,12 +4565,19 @@ const struct csky_opcode csky_v2_opcodes[] =
> OPCODE_INFO1 (0xe8400000,
> (0_15, COND16b, OPRND_SHIFT_1_BIT)),
> CSKYV2_ISA_1E2),
> +#undef _RELAX
> +#undef _RELOC16
> +#define _RELAX 0
> +#define _RELOC16 0
> + OP32 ("bnezad",
> + OPCODE_INFO2 (0xe8200000,
> + (16_20, AREG, OPRND_SHIFT_0_BIT),
> + (0_15, COND16b, OPRND_SHIFT_1_BIT)),
> + CSKYV2_ISA_3E3R2),
> #undef _RELOC16
> #undef _RELOC32
> -#undef _RELAX
> #define _RELOC16 0
> #define _RELOC32 0
> -#define _RELAX 0
> #undef _TRANSFER
> #define _TRANSFER 1
> OP16_WITH_WORK ("jbr",
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