assorted PPC questions

Jan Beulich jbeulich@suse.com
Tue Aug 18 08:12:52 GMT 2020


On 18.08.2020 02:10, Alan Modra wrote:
> On Mon, Aug 17, 2020 at 04:38:20PM +0200, Jan Beulich wrote:
>> On 17.08.2020 15:28, Alan Modra wrote:
>>> On Mon, Aug 17, 2020 at 10:19:28AM +0200, Jan Beulich wrote:
>>>> On 11.08.2020 11:02, Alan Modra wrote:
>>>>> On Wed, Aug 05, 2020 at 09:38:35AM +0200, Jan Beulich wrote:
>>>>>> Wouldn't availability of pseudos implying %cr0 as first (i.e.
>>>>>> destination) operand better be consistent throughout the opcode set?
>>>>>
>>>>> Are you saying every instruction ought to have a record bit?  ie. that
>>>>> there ought to be xxx. for every xxx?
>>>>
>>>> No, the question wasn't about the . suffix. Instead what I'm wondering
>>>> is why CMP*, VCMP*, and XVTLSBB have pseudos with the first operand
>>>> omitted (implying %cr0), while e.g. FCMP* doesn't (and there are quite
>>>> a few more).
>>>
>>> I'm not sure.  Possibly because you might expect that with a fcmpu
>>> form that allowed the BF field to be omitted, the implied CR field
>>> should be cr1 in line with with the record form of other fp insns,
>>> eg. fmr. sets cr1.  That conflicts with the general rule that an
>>> omitted field has a zero value.  (Yes, we now have a few exceptions,
>>> see *invalid < 0 tests in ppc-opc.c)
>>
>> Well, then maybe FCMP* was a bad example. What about CMPRB? Or possibly
>> some vector-scalar insns like xscmp*?
> 
> I'm going to say that the vector-scalar instructions are floating
> point instructions, but yes, it does seem like cmprb and cmpeqb could
> allow an optional BF.

I suppose this want to be spelled out in the ISA doc first, before
you want to add it to gas?

> Hmm, I gave vcmpsq and xvtlsbb an optional BF.  Since the record form
> of vector instructions set CR6, that was probably wrong.  Peter, do
> you agree with the following?
> 
> opcodes/
> 	* ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq
> 	and xvtlsbb.

vcmpuq as well then I guess?

Jan


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