[PATCH] aarch64: Add support for MPAM system registers

[Alex Coplan]

Hello,

This patch adds support for the system registers introduced in the
Armv8-A MPAM extension.

See https://developer.arm.com/documentation/ddi0598/latest for the
Arm ARM supplement documenting this extension.

Testing:
 * Regression tested on aarch64-none-elf.

OK for master?

Thanks,
Alex

---

gas/ChangeLog:

2020-08-10  Alex Coplan  <alex.coplan@arm.com>

	* testsuite/gas/aarch64/mpam-bad.d: New test.
	* testsuite/gas/aarch64/mpam-bad.l: Error output.
	* testsuite/gas/aarch64/mpam-bad.s: Input.
	* testsuite/gas/aarch64/mpam.d: New test.
	* testsuite/gas/aarch64/mpam.s: Input.

opcodes/ChangeLog:

2020-08-10  Alex Coplan  <alex.coplan@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.


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diff --git a/gas/testsuite/gas/aarch64/mpam-bad.d b/gas/testsuite/gas/aarch64/mpam-bad.d
new file mode 100644
index 00000000000..935db32a6e9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/mpam-bad.d
@@ -0,0 +1,2 @@
+#source: mpam-bad.s
+#warning_output: mpam-bad.l
diff --git a/gas/testsuite/gas/aarch64/mpam-bad.l b/gas/testsuite/gas/aarch64/mpam-bad.l
new file mode 100644
index 00000000000..49e282b14db
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/mpam-bad.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Warning: specified register cannot be written to at operand 1 -- `msr mpamidr_el1,x0'
diff --git a/gas/testsuite/gas/aarch64/mpam-bad.s b/gas/testsuite/gas/aarch64/mpam-bad.s
new file mode 100644
index 00000000000..022a83e286e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/mpam-bad.s
@@ -0,0 +1 @@
+msr mpamidr_el1, x0
diff --git a/gas/testsuite/gas/aarch64/mpam.d b/gas/testsuite/gas/aarch64/mpam.d
new file mode 100644
index 00000000000..58f4782175a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/mpam.d
@@ -0,0 +1,38 @@
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d538a520 	mrs	x0, mpam0_el1
+.*:	d518a520 	msr	mpam0_el1, x0
+.*:	d538a500 	mrs	x0, mpam1_el1
+.*:	d518a500 	msr	mpam1_el1, x0
+.*:	d53da500 	mrs	x0, mpam1_el12
+.*:	d51da500 	msr	mpam1_el12, x0
+.*:	d53ca500 	mrs	x0, mpam2_el2
+.*:	d51ca500 	msr	mpam2_el2, x0
+.*:	d53ea500 	mrs	x0, mpam3_el3
+.*:	d51ea500 	msr	mpam3_el3, x0
+.*:	d53ca400 	mrs	x0, mpamhcr_el2
+.*:	d51ca400 	msr	mpamhcr_el2, x0
+.*:	d538a480 	mrs	x0, mpamidr_el1
+.*:	d53ca600 	mrs	x0, mpamvpm0_el2
+.*:	d51ca600 	msr	mpamvpm0_el2, x0
+.*:	d53ca620 	mrs	x0, mpamvpm1_el2
+.*:	d51ca620 	msr	mpamvpm1_el2, x0
+.*:	d53ca640 	mrs	x0, mpamvpm2_el2
+.*:	d51ca640 	msr	mpamvpm2_el2, x0
+.*:	d53ca660 	mrs	x0, mpamvpm3_el2
+.*:	d51ca660 	msr	mpamvpm3_el2, x0
+.*:	d53ca680 	mrs	x0, mpamvpm4_el2
+.*:	d51ca680 	msr	mpamvpm4_el2, x0
+.*:	d53ca6a0 	mrs	x0, mpamvpm5_el2
+.*:	d51ca6a0 	msr	mpamvpm5_el2, x0
+.*:	d53ca6c0 	mrs	x0, mpamvpm6_el2
+.*:	d51ca6c0 	msr	mpamvpm6_el2, x0
+.*:	d53ca6e0 	mrs	x0, mpamvpm7_el2
+.*:	d51ca6e0 	msr	mpamvpm7_el2, x0
+.*:	d53ca420 	mrs	x0, mpamvpmv_el2
+.*:	d51ca420 	msr	mpamvpmv_el2, x0
diff --git a/gas/testsuite/gas/aarch64/mpam.s b/gas/testsuite/gas/aarch64/mpam.s
new file mode 100644
index 00000000000..507a49f1b34
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/mpam.s
@@ -0,0 +1,31 @@
+mrs x0, mpam0_el1
+msr mpam0_el1, x0
+mrs x0, mpam1_el1
+msr mpam1_el1, x0
+mrs x0, mpam1_el12
+msr mpam1_el12, x0
+mrs x0, mpam2_el2
+msr mpam2_el2, x0
+mrs x0, mpam3_el3
+msr mpam3_el3, x0
+mrs x0, mpamhcr_el2
+msr mpamhcr_el2, x0
+mrs x0, mpamidr_el1
+mrs x0, mpamvpm0_el2
+msr mpamvpm0_el2, x0
+mrs x0, mpamvpm1_el2
+msr mpamvpm1_el2, x0
+mrs x0, mpamvpm2_el2
+msr mpamvpm2_el2, x0
+mrs x0, mpamvpm3_el2
+msr mpamvpm3_el2, x0
+mrs x0, mpamvpm4_el2
+msr mpamvpm4_el2, x0
+mrs x0, mpamvpm5_el2
+msr mpamvpm5_el2, x0
+mrs x0, mpamvpm6_el2
+msr mpamvpm6_el2, x0
+mrs x0, mpamvpm7_el2
+msr mpamvpm7_el2, x0
+mrs x0, mpamvpmv_el2
+msr mpamvpmv_el2, x0
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 148ffb7bde6..f268bc24e57 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4241,6 +4241,23 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   SR_V8_4 ("sder32_el2",	CPENC (3,4,C1,C3,1),	0),
   SR_V8_4 ("vncr_el2",		CPENC (3,4,C2,C2,0),	0),
 
+  SR_CORE ("mpam0_el1",		CPENC (3,0,C10,C5,1),	0),
+  SR_CORE ("mpam1_el1",		CPENC (3,0,C10,C5,0),	0),
+  SR_CORE ("mpam1_el12",	CPENC (3,5,C10,C5,0),	0),
+  SR_CORE ("mpam2_el2",		CPENC (3,4,C10,C5,0),	0),
+  SR_CORE ("mpam3_el3",		CPENC (3,6,C10,C5,0),	0),
+  SR_CORE ("mpamhcr_el2",	CPENC (3,4,C10,C4,0),	0),
+  SR_CORE ("mpamidr_el1",	CPENC (3,0,C10,C4,4),	F_REG_READ),
+  SR_CORE ("mpamvpm0_el2",	CPENC (3,4,C10,C6,0),	0),
+  SR_CORE ("mpamvpm1_el2",	CPENC (3,4,C10,C6,1),	0),
+  SR_CORE ("mpamvpm2_el2",	CPENC (3,4,C10,C6,2),	0),
+  SR_CORE ("mpamvpm3_el2",	CPENC (3,4,C10,C6,3),	0),
+  SR_CORE ("mpamvpm4_el2",	CPENC (3,4,C10,C6,4),	0),
+  SR_CORE ("mpamvpm5_el2",	CPENC (3,4,C10,C6,5),	0),
+  SR_CORE ("mpamvpm6_el2",	CPENC (3,4,C10,C6,6),	0),
+  SR_CORE ("mpamvpm7_el2",	CPENC (3,4,C10,C6,7),	0),
+  SR_CORE ("mpamvpmv_el2",	CPENC (3,4,C10,C4,1),	0),
+
   { 0, CPENC (0,0,0,0,0), 0, 0 }
 };