[Patch, AArch64, Binutils] Add missing TSB instruction

[Sudakshina Das]

Hi

This patch implements the TSB instructions:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/tsb-csync-trace-synchronization-barrier
Since TSB and PSB both use the same (and only) argument "CSYNC", this patch reuses
it for TSB. However, the same argument would imply different value for CRm:Op2 which are anyway
fixed values, so I have diverted the inserter/extracter function to dummy versions instead of the
"hint" version. The operand checker part still uses the existing infratructure for
 AARCH64_OPND_BARRIER_PSB to make sure the operand is parsed correctly.

Build and regression tested on aarch64-none-linux-gnu.
Is this ok for trunk?

Thanks
Sudi
PS: I have not added the regenerated files to the patch to make it easier for review. I will add them
to the final commit.

gas/ChangeLog:

2020-xx-xx  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_barrier_psb): Update error messages
	to include TSB.
	* testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests.
	* testsuite/gas/aarch64/system-2.s: Add new tsb tests.
	* testsuite/gas/aarch64/system.d: Update.

opcodes/ChangeLog:

2020-xx-xx  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm.c (aarch64_ins_none): New.
	* aarch64-asm.h (ins_none): New declaration.
	* aarch64-dis.c (aarch64_ext_none): New.
	* aarch64-dis.h (ext_none): New declaration.
	* aarch64-opc.c (aarch64_print_operand): Update case for
	AARCH64_OPND_BARRIER_PSB.
	* aarch64-tbl.h (aarch64_opcode_table): Add tsb.
	(AARCH64_OPERANDS): Update inserter/extracter for
	AARCH64_OPND_BARRIER_PSB to use new dummy functions.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.






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