[RFC][PATCH 0/2] Add RISC-V cpu description and sim

[Jim Wilson]

On Wed, Sep 11, 2019 at 9:51 AM Edward Jones <ed.jones@embecosm.com> wrote:
> We're looking to add a cpu description for the riscv architecture
> plus a simulator port. The simulator has support for rv{32,64}imacfd
> and is capable of running small programs compiled against newlib.

I don't see the other two parts of the patch, but maybe they will turn
up tomorrow.

Incidentally, we have an existing gdb sim port originally written by
Mike Frysinger (vapier), with additions from Kito Cheng and myself,
which was implemented the traditional way, by hand.  I haven't pushed
to upstream this on the assumption that the cgen sim port from
Embecosm might be more useful and more maintainable.  The existing sim
port is known to work well enough to run the gcc testsuite, but
toolchain uses qemu by default, so I don't think that anyone other
than Kito and myself are using it, and we don't use it very much.
https://github.com/riscv/riscv-binutils-gdb/tree/fsf-gdb-with-sim/sim/riscv

I am concerned that any attempt to replace the current assembler is
likely to cause trouble though, as a lot of work has gone into the
existing one to get a lot of features and edge cases right.  There is
nothing important depending on the simulator though, so replacing that
should not cause trouble.  The disassembler is kind of in the middle,
there are a few things depending on it, and a few interesting features
in it people rely on, but probably few people will notice if it
changes.

I'll need to see the other two parts of the patch series, and time to
review them, to comment further.

Jim