[PATCH v2 8.5/9] x86-64: also support MOVSXD with 16-bit destination
Jan Beulich
jbeulich@suse.com
Mon Oct 28 08:09:00 GMT 2019
While not very useful, both Intel's and AMD's documentation mention the
case. Unfortunately the behavior differs in how wide of a source
(memory) operand is read. Therefore introduce two respective templates.
gas/
2019-10-XX Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-amd64.s,
testsuite/gas/i386/x86-64-amd64.d: New.
testsuite/gas/i386/i386.exp: Run new test.
* testsuite/gas/i386/x86-64-intel64.s: Add -mintel64 command
line option and movsxd tests.
* testsuite/gas/i386/ilp32/x86-64-intel64.d,
testsuite/gas/i386/movx64.l,
testsuite/gas/i386/x86-64-intel64.d: Adjust expectations.
opcodes/
2019-10-XX Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (movsxd): New patterns with 16-bit destination.
* i386-tbl.h: Re-generate.
---
v2: New. (I'm sorry - I can't seem to be able to count correctly today,
and hence I missed this patch when composing the cover letter.)
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -644,6 +644,7 @@ if [expr ([istarget "i*86-*-*"] || [ista
run_dump_test "x86-64-addr32"
run_dump_test "x86-64-addr32-intel"
run_dump_test "x86-64-opcode"
+ run_dump_test "x86-64-amd64"
run_dump_test "x86-64-intel64"
if { ! [istarget "*-*-*cygwin*"] && ![istarget "*-*-mingw*"] } then {
run_dump_test "x86-64-pcrel"
--- a/gas/testsuite/gas/i386/ilp32/x86-64-intel64.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-intel64.d
@@ -1,11 +1,5 @@
#source: ../x86-64-intel64.s
+#as: -mintel64
#objdump: -dw
#name: x86-64 (ILP32) Intel64
-
-.*: +file format .*
-
-Disassembly of section .text:
-0+ <_start>:
-[ ]*[a-f0-9]+: 0f 05 syscall
-[ ]*[a-f0-9]+: 0f 07 sysret
-#pass
+#dump: ../x86-64-intel64.d
--- a/gas/testsuite/gas/i386/movx64.l
+++ b/gas/testsuite/gas/i386/movx64.l
@@ -88,7 +88,7 @@
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxd %al, %cx
[ ]*[1-9][0-9]*[ ]+movsxd %ax, %cx
-[ ]*[1-9][0-9]*[ ]+movsxd %eax, %cx
+[ ]*[1-9][0-9]* \?\?\?\? 6663C8[ ]+movsxd %eax, %cx
[ ]*[1-9][0-9]*[ ]+movsxd %rax, %cx
[ ]*[1-9][0-9]*[ ]*
[ ]*[1-9][0-9]*[ ]+movsxd %al, %ecx
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amd64.d
@@ -0,0 +1,12 @@
+#as: -mamd64
+#objdump: -dw
+#name: x86-64 AMD64
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]+66 63 c8[ ]+movslq %eax,%cx
+[ ]*[a-f0-9]+:[ ]+66 63 08[ ]+movslq \(%rax\),%cx
+[ ]*[a-f0-9]+:[ ]+66 63 08[ ]+movslq \(%rax\),%cx
+#pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amd64.s
@@ -0,0 +1,8 @@
+# Check AMD64
+
+ .text
+_start:
+ .intel_syntax noprefix
+ movsxd cx, eax
+ movsxd cx, [rax]
+ movsxd cx, dword ptr [rax]
--- a/gas/testsuite/gas/i386/x86-64-intel64.d
+++ b/gas/testsuite/gas/i386/x86-64-intel64.d
@@ -1,3 +1,4 @@
+#as: -mintel64
#objdump: -dw
#name: x86-64 Intel64
@@ -7,4 +8,7 @@ Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+: 0f 05 syscall
[ ]*[a-f0-9]+: 0f 07 sysret
+[ ]*[a-f0-9]+: 66 63 c8 movslq %eax,%cx
+[ ]*[a-f0-9]+: 66 63 08 movslq \(%rax\),%cx
+[ ]*[a-f0-9]+: 66 63 08 movslq \(%rax\),%cx
#pass
--- a/gas/testsuite/gas/i386/x86-64-intel64.s
+++ b/gas/testsuite/gas/i386/x86-64-intel64.s
@@ -5,3 +5,8 @@
_start:
syscall
sysret
+
+ .intel_syntax noprefix
+ movsxd cx, ax
+ movsxd cx, [rax]
+ movsxd cx, word ptr [rax]
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -104,10 +104,13 @@ movswl, 2, 0xfbf, None, 2, Cpu386, Modrm
movsbq, 2, 0xfbe, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex, Reg64 }
movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex, Reg64 }
movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 }
-// Intel Syntax next 3 insns
+// Intel Syntax next 5 insns (the two 16-bit variants at the end aren't
+// particularly useful, but the specifications mention them)
movsx, 2, 0xfbe, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
+movsxd, 2, 0x63, None, 1, Cpu64, AMD64|Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg16 }
+movsxd, 2, 0x63, None, 1, Cpu64, Intel64|Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Unspecified|BaseIndex, Reg16 }
// Move with zero extend.
movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
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