Hi,
Changed '+i8mm' to be default for v8.6-A targets.
Updated ChangeLog:
gas/ChangeLog:
2019-09-05 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-aarch64.c: Add new arch fetures to suppport the mm extension.
(parse_operands): Add new operand.
* testsuite/gas/aarch64/i8mm.s: New test.
* testsuite/gas/aarch64/i8mm.d: New test.
* testsuite/gas/aarch64/f32mm.s: New test.
* testsuite/gas/aarch64/f32mm.d: New test.
* testsuite/gas/aarch64/f64mm.s: New test.
* testsuite/gas/aarch64/f64mm.d: New test.
* testsuite/gas/aarch64/sve-movprfx-mm.s: New test.
* testsuite/gas/aarch64/sve-movprfx-mm.d: New test.
include/ChangeLog:
2019-09-05 Mihail Ionescu <mihail.ionescu@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_I8MM): New.
(AARCH64_FEATURE_F32MM): New.
(AARCH64_FEATURE_F64MM): New.
(AARCH64_OPND_SVE_ADDR_RI_S4x32): New.
(enum aarch64_insn_class): Add new instruction class "aarch64_misc" for
instructions that do not require special handling.
opcodes/ChangeLog:
2019-09-05 Mihail Ionescu <mihail.ionescu@arm.com>
* aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
aarch64_feature_f64mm): New feature sets.
(INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
instructions.
(AARCH64_ARCH_V8_6): Add i8mm.
(I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
macros.
(QL_MMLA64, OP_SVE_SBB): New qualifiers.
(OP_SVE_QQQ): New qualifier.
(INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
the movprfx constraint.
(aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
(aarch64_opcode_table): Define new instructions smmla,
ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod
. uzip{1/2}, trn{1/2}.
* aarch64-opc.c (operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_ADDR_RI_S4x32.
(aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
* aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
Account for new instructions.
* opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
S4x32 operand.
* aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
Regards,
Mihail
On 10/29/2019 03:20 PM, Mihail Ionescu wrote:
> Hi,
>
> This patch is part of a series that adds support for Armv8.6-A
> (Matrix Multiply and BFloat16 extensions) to binutils.
>
> This patch introduces the Matrix Multiply (Int8, F32, F64) extensions
> to the aarch64 backend.
>
> The following instructions are added: {s/u}mmla, usmmla, {us/su}dot,
> fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}.
>
> gas/ChangeLog:
>
> 2019-10-29 Mihail Ionescu <mihail.ionescu@arm.com>
>
> * config/tc-aarch64.c: Add new arch fetures to suppport the mm extension.
> (parse_operands): Add new operand.
> * testsuite/gas/aarch64/i8mm.s: New test.
> * testsuite/gas/aarch64/i8mm.d: New test.
> * testsuite/gas/aarch64/f32mm.s: New test.
> * testsuite/gas/aarch64/f32mm.d: New test.
> * testsuite/gas/aarch64/f64mm.s: New test.
> * testsuite/gas/aarch64/f64mm.d: New test.
> * testsuite/gas/aarch64/sve-movprfx-mm.s: New test.
> * testsuite/gas/aarch64/sve-movprfx-mm.d: New test.
>
> include/ChangeLog:
>
> 2019-10-29 Mihail Ionescu <mihail.ionescu@arm.com>
>
> * opcode/aarch64.h (AARCH64_FEATURE_I8MM): New.
> (AARCH64_FEATURE_F32MM): New.
> (AARCH64_FEATURE_F64MM): New.
> (AARCH64_OPND_SVE_ADDR_RI_S4x32): New.
> (enum aarch64_insn_class): Add new instruction class "aarch64_misc" for
> instructions that do not require special handling.
>
> opcodes/ChangeLog:
>
> 2019-10-29 Mihail Ionescu <mihail.ionescu@arm.com>
>
> * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
> aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
> aarch64_feature_f64mm): New feature sets.
> (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
> F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
> instructions.
> (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
> macros.
> (QL_MMLA64, OP_SVE_SBB): New qualifiers.
> (OP_SVE_QQQ): New qualifier.
> (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
> F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
> the movprfx constraint.
> (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
> (aarch64_opcode_table): Define new instructions smmla,
> ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
> uzip{1/2}, trn{1/2}.
> * aarch64-opc.c (operand_general_constraint_met_p): Handle
> AARCH64_OPND_SVE_ADDR_RI_S4x32.
> (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
> * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
> Account for new instructions.
> * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
> S4x32 operand.
> * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
>
> Regression tested on arm-none-eabi.
>
> Is it ok for trunk?
>
>
> Regards,
> Mihail
>
-------------- next part --------------
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index dbf51c1f3212fd2c1fe116e23a3ee89a85e95fd1..ba8dd30395f0195536b18bf391524bfc9b53fcdd 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6419,6 +6419,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
+ case AARCH64_OPND_SVE_ADDR_RI_S4x32:
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
@@ -9044,6 +9045,12 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0)},
{"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0),
AARCH64_ARCH_NONE},
+ {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0),
+ AARCH64_ARCH_NONE},
+ {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM, 0),
+ AARCH64_ARCH_NONE},
+ {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM, 0),
+ AARCH64_ARCH_NONE},
{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 4cb94872daa647e543c1c67b486e71de21dcb425..056f23decc1bc3fa67698b2ba983510fdc45194e 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -144,6 +144,12 @@ automatically cause those extensions to be disabled.
@multitable @columnfractions .12 .17 .17 .54
@headitem Extension @tab Minimum Architecture @tab Enabled by default
@tab Description
+@item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
+ @tab Enable Int8 Matrix Multiply extension.
+@item @code{f32mm} @tab ARMv8.2-A @tab No
+ @tab Enable F32 Matrix Multiply extension.
+@item @code{f64mm} @tab ARMv8.2-A @tab No
+ @tab Enable F64 Matrix Multiply extension.
@item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
@tab Enable BFloat16 extension.
@item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
diff --git a/gas/testsuite/gas/aarch64/f32mm.d b/gas/testsuite/gas/aarch64/f32mm.d
new file mode 100644
index 0000000000000000000000000000000000000000..8f1cdffa5ec3973c6208d4f081cc26b2251c3eca
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f32mm.d
@@ -0,0 +1,11 @@
+#as: -march=armv8.6-a+sve+f32mm
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <\.text>:
+ *[0-9a-f]+: 64bbe6b1 fmmla z17\.s, z21\.s, z27\.s
+ *[0-9a-f]+: 64a0e400 fmmla z0\.s, z0\.s, z0\.s
diff --git a/gas/testsuite/gas/aarch64/f32mm.s b/gas/testsuite/gas/aarch64/f32mm.s
new file mode 100644
index 0000000000000000000000000000000000000000..6e6b32b0bf72391edf229d30d7fbc1bfbf98bb63
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f32mm.s
@@ -0,0 +1,12 @@
+/* The instructions with non-zero register numbers are there to ensure we have
+ the correct argument positioning (i.e. check that the first argument is at
+ the end of the word etc).
+ The instructions with all-zero register numbers are to ensure the previous
+ encoding didn't just "happen" to fit -- so that if we change the registers
+ that changes the correct part of the word.
+ Each of the numbered patterns begin and end with a 1, so we can replace
+ them with all-zeros and see the entire range has changed. */
+
+// SVE
+fmmla z17.s, z21.s, z27.s
+fmmla z0.s, z0.s, z0.s
diff --git a/gas/testsuite/gas/aarch64/f64mm.d b/gas/testsuite/gas/aarch64/f64mm.d
new file mode 100644
index 0000000000000000000000000000000000000000..9540c136c82cfaeffa326121d643ca37de714aa2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f64mm.d
@@ -0,0 +1,62 @@
+#as: -march=armv8.6-a+sve+f64mm
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <\.text>:
+ *[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d
+ *[0-9a-f]+: 64c0e400 fmmla z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+: a43b17f1 ld1rob {z17\.b}, p5/z, \[sp, x27\]
+ *[0-9a-f]+: a42003e0 ld1rob {z0\.b}, p0/z, \[sp, x0\]
+ *[0-9a-f]+: a4bb17f1 ld1roh {z17\.h}, p5/z, \[sp, x27\]
+ *[0-9a-f]+: a4a003e0 ld1roh {z0\.h}, p0/z, \[sp, x0\]
+ *[0-9a-f]+: a53b17f1 ld1row {z17\.s}, p5/z, \[sp, x27\]
+ *[0-9a-f]+: a52003e0 ld1row {z0\.s}, p0/z, \[sp, x0\]
+ *[0-9a-f]+: a5bb17f1 ld1rod {z17\.d}, p5/z, \[sp, x27\]
+ *[0-9a-f]+: a5a003e0 ld1rod {z0\.d}, p0/z, \[sp, x0\]
+ *[0-9a-f]+: a43b1411 ld1rob {z17\.b}, p5/z, \[x0, x27\]
+ *[0-9a-f]+: a4200000 ld1rob {z0\.b}, p0/z, \[x0, x0\]
+ *[0-9a-f]+: a4bb1411 ld1roh {z17\.h}, p5/z, \[x0, x27\]
+ *[0-9a-f]+: a4a00000 ld1roh {z0\.h}, p0/z, \[x0, x0\]
+ *[0-9a-f]+: a53b1411 ld1row {z17\.s}, p5/z, \[x0, x27\]
+ *[0-9a-f]+: a5200000 ld1row {z0\.s}, p0/z, \[x0, x0\]
+ *[0-9a-f]+: a5bb1411 ld1rod {z17\.d}, p5/z, \[x0, x27\]
+ *[0-9a-f]+: a5a00000 ld1rod {z0\.d}, p0/z, \[x0, x0\]
+ *[0-9a-f]+: a42037f1 ld1rob {z17\.b}, p5/z, \[sp\]
+ *[0-9a-f]+: a42723e0 ld1rob {z0\.b}, p0/z, \[sp, #224\]
+ *[0-9a-f]+: a42823e0 ld1rob {z0\.b}, p0/z, \[sp, #-256\]
+ *[0-9a-f]+: a4a037f1 ld1roh {z17\.h}, p5/z, \[sp\]
+ *[0-9a-f]+: a4a723e0 ld1roh {z0\.h}, p0/z, \[sp, #224\]
+ *[0-9a-f]+: a4a823e0 ld1roh {z0\.h}, p0/z, \[sp, #-256\]
+ *[0-9a-f]+: a52037f1 ld1row {z17\.s}, p5/z, \[sp\]
+ *[0-9a-f]+: a52723e0 ld1row {z0\.s}, p0/z, \[sp, #224\]
+ *[0-9a-f]+: a52823e0 ld1row {z0\.s}, p0/z, \[sp, #-256\]
+ *[0-9a-f]+: a5a037f1 ld1rod {z17\.d}, p5/z, \[sp\]
+ *[0-9a-f]+: a5a723e0 ld1rod {z0\.d}, p0/z, \[sp, #224\]
+ *[0-9a-f]+: a5a823e0 ld1rod {z0\.d}, p0/z, \[sp, #-256\]
+ *[0-9a-f]+: a4203411 ld1rob {z17\.b}, p5/z, \[x0\]
+ *[0-9a-f]+: a4272000 ld1rob {z0\.b}, p0/z, \[x0, #224\]
+ *[0-9a-f]+: a4282000 ld1rob {z0\.b}, p0/z, \[x0, #-256\]
+ *[0-9a-f]+: a4a03411 ld1roh {z17\.h}, p5/z, \[x0\]
+ *[0-9a-f]+: a4a72000 ld1roh {z0\.h}, p0/z, \[x0, #224\]
+ *[0-9a-f]+: a4a82000 ld1roh {z0\.h}, p0/z, \[x0, #-256\]
+ *[0-9a-f]+: a5203411 ld1row {z17\.s}, p5/z, \[x0\]
+ *[0-9a-f]+: a5272000 ld1row {z0\.s}, p0/z, \[x0, #224\]
+ *[0-9a-f]+: a5282000 ld1row {z0\.s}, p0/z, \[x0, #-256\]
+ *[0-9a-f]+: a5a03411 ld1rod {z17\.d}, p5/z, \[x0\]
+ *[0-9a-f]+: a5a72000 ld1rod {z0\.d}, p0/z, \[x0, #224\]
+ *[0-9a-f]+: a5a82000 ld1rod {z0\.d}, p0/z, \[x0, #-256\]
+ *[0-9a-f]+: 05a502b1 zip1 z17\.q, z21\.q, z5\.q
+ *[0-9a-f]+: 05a00000 zip1 z0\.q, z0\.q, z0\.q
+ *[0-9a-f]+: 05a506b1 zip2 z17\.q, z21\.q, z5\.q
+ *[0-9a-f]+: 05a00400 zip2 z0\.q, z0\.q, z0\.q
+ *[0-9a-f]+: 05a50ab1 uzip1 z17\.q, z21\.q, z5\.q
+ *[0-9a-f]+: 05a00800 uzip1 z0\.q, z0\.q, z0\.q
+ *[0-9a-f]+: 05a50eb1 uzip2 z17\.q, z21\.q, z5\.q
+ *[0-9a-f]+: 05a00c00 uzip2 z0\.q, z0\.q, z0\.q
+ *[0-9a-f]+: 05a51ab1 trn1 z17\.q, z21\.q, z5\.q
+ *[0-9a-f]+: 05a01800 trn1 z0\.q, z0\.q, z0\.q
+ *[0-9a-f]+: 05a51eb1 trn2 z17\.q, z21\.q, z5\.q
+ *[0-9a-f]+: 05a01c00 trn2 z0\.q, z0\.q, z0\.q
diff --git a/gas/testsuite/gas/aarch64/f64mm.s b/gas/testsuite/gas/aarch64/f64mm.s
new file mode 100644
index 0000000000000000000000000000000000000000..fcf662be300311182f44ddd7ccc1ef9ea1e24dd4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f64mm.s
@@ -0,0 +1,71 @@
+/* The instructions with non-zero register numbers are there to ensure we have
+ the correct argument positioning (i.e. check that the first argument is at
+ the end of the word etc).
+ The instructions with all-zero register numbers are to ensure the previous
+ encoding didn't just "happen" to fit -- so that if we change the registers
+ that changes the correct part of the word.
+ Each of the numbered patterns begin and end with a 1, so we can replace
+ them with all-zeros and see the entire range has changed. */
+
+// SVE
+fmmla z17.d, z21.d, z27.d
+fmmla z0.d, z0.d, z0.d
+
+ld1rob { z17.b }, p5/z, [sp, x27]
+ld1rob { z0.b }, p0/z, [sp, x0]
+ld1roh { z17.h }, p5/z, [sp, x27]
+ld1roh { z0.h }, p0/z, [sp, x0]
+ld1row { z17.s }, p5/z, [sp, x27]
+ld1row { z0.s }, p0/z, [sp, x0]
+ld1rod { z17.d }, p5/z, [sp, x27]
+ld1rod { z0.d }, p0/z, [sp, x0]
+
+ld1rob { z17.b }, p5/z, [x0, x27]
+ld1rob { z0.b }, p0/z, [x0, x0]
+ld1roh { z17.h }, p5/z, [x0, x27]
+ld1roh { z0.h }, p0/z, [x0, x0]
+ld1row { z17.s }, p5/z, [x0, x27]
+ld1row { z0.s }, p0/z, [x0, x0]
+ld1rod { z17.d }, p5/z, [x0, x27]
+ld1rod { z0.d }, p0/z, [x0, x0]
+
+ld1rob { z17.b }, p5/z, [sp, #0]
+ld1rob { z0.b }, p0/z, [sp, #224]
+ld1rob { z0.b }, p0/z, [sp, #-256]
+ld1roh { z17.h }, p5/z, [sp, #0]
+ld1roh { z0.h }, p0/z, [sp, #224]
+ld1roh { z0.h }, p0/z, [sp, #-256]
+ld1row { z17.s }, p5/z, [sp, #0]
+ld1row { z0.s }, p0/z, [sp, #224]
+ld1row { z0.s }, p0/z, [sp, #-256]
+ld1rod { z17.d }, p5/z, [sp, #0]
+ld1rod { z0.d }, p0/z, [sp, #224]
+ld1rod { z0.d }, p0/z, [sp, #-256]
+
+ld1rob { z17.b }, p5/z, [x0, #0]
+ld1rob { z0.b }, p0/z, [x0, #224]
+ld1rob { z0.b }, p0/z, [x0, #-256]
+ld1roh { z17.h }, p5/z, [x0, #0]
+ld1roh { z0.h }, p0/z, [x0, #224]
+ld1roh { z0.h }, p0/z, [x0, #-256]
+ld1row { z17.s }, p5/z, [x0, #0]
+ld1row { z0.s }, p0/z, [x0, #224]
+ld1row { z0.s }, p0/z, [x0, #-256]
+ld1rod { z17.d }, p5/z, [x0, #0]
+ld1rod { z0.d }, p0/z, [x0, #224]
+ld1rod { z0.d }, p0/z, [x0, #-256]
+
+zip1 z17.q, z21.q, z5.q
+zip1 z0.q, z0.q, z0.q
+zip2 z17.q, z21.q, z5.q
+zip2 z0.q, z0.q, z0.q
+
+uzip1 z17.q, z21.q, z5.q
+uzip1 z0.q, z0.q, z0.q
+uzip2 z17.q, z21.q, z5.q
+uzip2 z0.q, z0.q, z0.q
+
+trn1 z17.q, z21.q, z5.q
+trn1 z0.q, z0.q, z0.q
+trn2 z17.q, z21.q, z5.q
+trn2 z0.q, z0.q, z0.q
diff --git a/gas/testsuite/gas/aarch64/i8mm.d b/gas/testsuite/gas/aarch64/i8mm.d
new file mode 100644
index 0000000000000000000000000000000000000000..14db65f7404ca383c2d57b3e2b9105b5424e38be
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/i8mm.d
@@ -0,0 +1,43 @@
+#as: -march=armv8.6-a+sve
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <\.text>:
+ *[0-9a-f]+: 451b9ab1 smmla z17\.s, z21\.b, z27\.b
+ *[0-9a-f]+: 45009800 smmla z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 45db9ab1 ummla z17\.s, z21\.b, z27\.b
+ *[0-9a-f]+: 45c09800 ummla z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 459b9ab1 usmmla z17\.s, z21\.b, z27\.b
+ *[0-9a-f]+: 45809800 usmmla z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 449b7ab1 usdot z17\.s, z21\.b, z27\.b
+ *[0-9a-f]+: 44807800 usdot z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 44bf1ab1 usdot z17\.s, z21\.b, z7\.b\[3\]
+ *[0-9a-f]+: 44b81800 usdot z0\.s, z0\.b, z0\.b\[3\]
+ *[0-9a-f]+: 44a71ab1 usdot z17\.s, z21\.b, z7\.b\[0\]
+ *[0-9a-f]+: 44a01800 usdot z0\.s, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 44bf1eb1 sudot z17\.s, z21\.b, z7\.b\[3\]
+ *[0-9a-f]+: 44b81c00 sudot z0\.s, z0\.b, z0\.b\[3\]
+ *[0-9a-f]+: 44a71eb1 sudot z17\.s, z21\.b, z7\.b\[0\]
+ *[0-9a-f]+: 44a01c00 sudot z0\.s, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 4e9ba6b1 smmla v17\.4s, v21\.16b, v27\.16b
+ *[0-9a-f]+: 4e9ba6b1 smmla v17\.4s, v21\.16b, v27\.16b
+ *[0-9a-f]+: 6e9ba6b1 ummla v17\.4s, v21\.16b, v27\.16b
+ *[0-9a-f]+: 6e80a400 ummla v0\.4s, v0\.16b, v0\.16b
+ *[0-9a-f]+: 4e80ac00 usmmla v0\.4s, v0\.16b, v0\.16b
+ *[0-9a-f]+: 4e9baeb1 usmmla v17\.4s, v21\.16b, v27\.16b
+ *[0-9a-f]+: 4e9b9eb1 usdot v17\.2s, v21\.8b, v27\.8b
+ *[0-9a-f]+: 4e809c00 usdot v0\.2s, v0\.8b, v0\.8b
+ *[0-9a-f]+: 4e9b9eb1 usdot v17\.2s, v21\.8b, v27\.8b
+ *[0-9a-f]+: 4e809c00 usdot v0\.2s, v0\.8b, v0\.8b
+ *[0-9a-f]+: 4fbbfab1 usdot v17\.2s, v21\.8b, v27\.4b\[3\]
+ *[0-9a-f]+: 4fa0f800 usdot v0\.2s, v0\.8b, v0\.4b\[3\]
+ *[0-9a-f]+: 4f9bf2b1 usdot v17\.2s, v21\.8b, v27\.4b\[0\]
+ *[0-9a-f]+: 4f80f000 usdot v0\.2s, v0\.8b, v0\.4b\[0\]
+ *[0-9a-f]+: 4f3bfab1 sudot v17\.2s, v21\.8b, v27\.4b\[3\]
+ *[0-9a-f]+: 4f20f800 sudot v0\.2s, v0\.8b, v0\.4b\[3\]
+ *[0-9a-f]+: 4f1bf2b1 sudot v17\.2s, v21\.8b, v27\.4b\[0\]
+ *[0-9a-f]+: 4f00f000 sudot v0\.2s, v0\.8b, v0\.4b\[0\]
diff --git a/gas/testsuite/gas/aarch64/i8mm.s b/gas/testsuite/gas/aarch64/i8mm.s
new file mode 100644
index 0000000000000000000000000000000000000000..38f871da331f47540dc31609ec132662c7a8f368
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/i8mm.s
@@ -0,0 +1,56 @@
+/* The instructions with non-zero register numbers are there to ensure we have
+ the correct argument positioning (i.e. check that the first argument is at
+ the end of the word etc).
+ The instructions with all-zero register numbers are to ensure the previous
+ encoding didn't just "happen" to fit -- so that if we change the registers
+ that changes the correct part of the word.
+ Each of the numbered patterns begin and end with a 1, so we can replace
+ them with all-zeros and see the entire range has changed. */
+
+// SVE
+smmla z17.s, z21.b, z27.b
+smmla z0.s, z0.b, z0.b
+
+ummla z17.s, z21.b, z27.b
+ummla z0.s, z0.b, z0.b
+
+usmmla z17.s, z21.b, z27.b
+usmmla z0.s, z0.b, z0.b
+
+usdot z17.s, z21.b, z27.b
+usdot z0.s, z0.b, z0.b
+
+usdot z17.s, z21.b, z7.b[3]
+usdot z0.s, z0.b, z0.b[3]
+usdot z17.s, z21.b, z7.b[0]
+usdot z0.s, z0.b, z0.b[0]
+
+sudot z17.s, z21.b, z7.b[3]
+sudot z0.s, z0.b, z0.b[3]
+sudot z17.s, z21.b, z7.b[0]
+sudot z0.s, z0.b, z0.b[0]
+
+// SIMD
+smmla v17.4s, v21.16b, v27.16b
+smmla v17.4s, v21.16b, v27.16b
+
+ummla v17.4s, v21.16b, v27.16b
+ummla v0.4s, v0.16b, v0.16b
+
+usmmla v0.4s, v0.16b, v0.16b
+usmmla v17.4s, v21.16b, v27.16b
+
+usdot v17.2s, v21.8b, v27.8b
+usdot v0.2s, v0.8b, v0.8b
+usdot v17.4s, v21.16b, v27.16b
+usdot v0.4s, v0.16b, v0.16b
+
+usdot v17.2s, v21.8b, v27.4b[3]
+usdot v0.2s, v0.8b, v0.4b[3]
+usdot v17.2s, v21.8b, v27.4b[0]
+usdot v0.2s, v0.8b, v0.4b[0]
+
+sudot v17.4s, v21.16b, v27.4b[3]
+sudot v0.4s, v0.16b, v0.4b[3]
+sudot v17.4s, v21.16b, v27.4b[0]
+sudot v0.4s, v0.16b, v0.4b[0]
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx-mm.d b/gas/testsuite/gas/aarch64/sve-movprfx-mm.d
new file mode 100644
index 0000000000000000000000000000000000000000..197f69fae84949bc73e3919ea01f3d730995b2ff
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-movprfx-mm.d
@@ -0,0 +1,24 @@
+#as: -march=armv8.6-a+f32mm+f64mm+sve
+#objdump: -dr
+
+.* file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <\.text>:
+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
+ *[0-9a-f]+: 451b9ab1 smmla z17\.s, z21\.b, z27\.b
+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
+ *[0-9a-f]+: 45db9ab1 ummla z17\.s, z21\.b, z27\.b
+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
+ *[0-9a-f]+: 459b9ab1 usmmla z17\.s, z21\.b, z27\.b
+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
+ *[0-9a-f]+: 449b7ab1 usdot z17\.s, z21\.b, z27\.b
+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
+ *[0-9a-f]+: 44bf1ab1 usdot z17\.s, z21\.b, z7\.b\[3\]
+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
+ *[0-9a-f]+: 44bf1eb1 sudot z17\.s, z21\.b, z7\.b\[3\]
+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
+ *[0-9a-f]+: 64bbe6b1 fmmla z17\.s, z21\.s, z27\.s
+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
+ *[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d
diff --git a/gas/testsuite/gas/aarch64/sve-movprfx-mm.s b/gas/testsuite/gas/aarch64/sve-movprfx-mm.s
new file mode 100644
index 0000000000000000000000000000000000000000..6af5844ccc3a8d5a0f2f672d7a575cfe88fa0f6e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-movprfx-mm.s
@@ -0,0 +1,25 @@
+/* MOVPRFX tests for matrix multiply instructions */
+
+movprfx z17, z0
+smmla z17.s, z21.b, z27.b
+
+movprfx z17, z0
+ummla z17.s, z21.b, z27.b
+
+movprfx z17, z0
+usmmla z17.s, z21.b, z27.b
+
+movprfx z17, z0
+usdot z17.s, z21.b, z27.b
+
+movprfx z17, z0
+usdot z17.s, z21.b, z7.b[3]
+
+movprfx z17, z0
+sudot z17.s, z21.b, z7.b[3]
+
+movprfx z17, z0
+fmmla z17.s, z21.s, z27.s
+
+movprfx z17, z0
+fmmla z17.d, z21.d, z27.d
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 4cda1e079e03a70a808a6c03e36dcfe221751919..d9f3d097c87ed04504040ffdff70c360f4113dea 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -91,6 +91,11 @@ typedef uint32_t aarch64_insn;
/* Transactional Memory Extension. */
#define AARCH64_FEATURE_TME 0x2000000000000ULL
+/* Matrix Multiply instructions */
+#define AARCH64_FEATURE_I8MM 0x10000000000000ULL
+#define AARCH64_FEATURE_F32MM 0x20000000000000ULL
+#define AARCH64_FEATURE_F64MM 0x40000000000000ULL
+
/* SVE2 instructions. */
#define AARCH64_FEATURE_SVE2 0x000000010
#define AARCH64_FEATURE_SVE2_AES 0x000000080
@@ -133,7 +138,8 @@ typedef uint32_t aarch64_insn;
| AARCH64_FEATURE_SSBS)
#define AARCH64_ARCH_V8_6 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \
AARCH64_FEATURE_V8_6 \
- | AARCH64_FEATURE_BFLOAT16)
+ | AARCH64_FEATURE_BFLOAT16 \
+ | AARCH64_FEATURE_I8MM)
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
@@ -322,6 +328,7 @@ enum aarch64_opnd
AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
+ AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */
AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
@@ -520,6 +527,7 @@ enum aarch64_opnd_qualifier
enum aarch64_insn_class
{
+ aarch64_misc,
addsub_carry,
addsub_ext,
addsub_imm,
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 20472ae43549fc1ee2f3e2c76539309ba888ed92..3fa081a6ea19c6709a5a3fb5e028b39db75aa95f 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -628,7 +628,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 28:
case 29:
case 30:
- case 162:
case 163:
case 164:
case 165:
@@ -638,7 +637,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 169:
case 170:
case 171:
- case 186:
+ case 172:
case 187:
case 188:
case 189:
@@ -647,8 +646,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 192:
case 193:
case 194:
- case 200:
- case 203:
+ case 195:
+ case 201:
+ case 204:
return aarch64_ins_regno (self, info, code, inst, errors);
case 14:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -660,7 +660,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 32:
case 33:
case 34:
- case 206:
+ case 207:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 35:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -694,9 +694,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 80:
case 81:
case 82:
- case 159:
- case 161:
- case 178:
+ case 160:
+ case 162:
case 179:
case 180:
case 181:
@@ -704,7 +703,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 183:
case 184:
case 185:
- case 205:
+ case 186:
+ case 206:
return aarch64_ins_imm (self, info, code, inst, errors);
case 43:
case 44:
@@ -714,10 +714,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 47:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 51:
- case 149:
+ case 150:
return aarch64_ins_fpimm (self, info, code, inst, errors);
case 68:
- case 157:
+ case 158:
return aarch64_ins_limm (self, info, code, inst, errors);
case 69:
return aarch64_ins_aimm (self, info, code, inst, errors);
@@ -727,11 +727,11 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_fbits (self, info, code, inst, errors);
case 73:
case 74:
- case 154:
+ case 155:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 75:
- case 153:
- case 155:
+ case 154:
+ case 156:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 76:
case 77:
@@ -774,22 +774,22 @@ aarch64_insert_operand (const aarch64_operand *self,
case 106:
return aarch64_ins_hint (self, info, code, inst, errors);
case 107:
- return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 108:
+ return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 109:
case 110:
case 111:
- return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 112:
- return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 113:
- return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 114:
+ return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 115:
case 116:
case 117:
- return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 118:
+ return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 119:
case 120:
case 121:
@@ -803,8 +803,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 129:
case 130:
case 131:
- return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 132:
+ return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 133:
case 134:
case 135:
@@ -812,52 +812,53 @@ aarch64_insert_operand (const aarch64_operand *self,
case 137:
case 138:
case 139:
- return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 140:
+ return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 141:
case 142:
case 143:
- return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 144:
- return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 145:
- return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 146:
- return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 147:
- return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 148:
+ return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ case 149:
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
- case 150:
- return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 151:
- return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 152:
+ return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ case 153:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
- case 156:
+ case 157:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
- case 158:
+ case 159:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
- case 160:
+ case 161:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
- case 172:
case 173:
case 174:
- return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 175:
+ return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 176:
case 177:
+ case 178:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
- case 195:
case 196:
case 197:
case 198:
case 199:
+ case 200:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
- case 201:
- return aarch64_ins_sve_index (self, info, code, inst, errors);
case 202:
- case 204:
+ return aarch64_ins_sve_index (self, info, code, inst, errors);
+ case 203:
+ case 205:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index cd1f6b91a931fc86f06786cad11c3a683d5ed0dd..a27f7245e12a1becd0e2670db6f41ad2e00fd80f 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -4285,21 +4285,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x0101xxxxx000x10xxxxxxxxxx
- mla. */
- return 2099;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0101xxxxx000010xxxxxxxxxx
+ mla. */
+ return 2099;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0111xxxxx000010xxxxxxxxxx
+ mla. */
+ return 2100;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 010001x0111xxxxx000x10xxxxxxxxxx
- mla. */
- return 2100;
+ 010001x01x1xxxxx000110xxxxxxxxxx
+ usdot. */
+ return 2394;
}
}
}
@@ -4348,21 +4359,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x0101xxxxx000x11xxxxxxxxxx
- mls. */
- return 2102;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0101xxxxx000011xxxxxxxxxx
+ mls. */
+ return 2102;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0111xxxxx000011xxxxxxxxxx
+ mls. */
+ return 2103;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 010001x0111xxxxx000x11xxxxxxxxxx
- mls. */
- return 2103;
+ 010001x01x1xxxxx000111xxxxxxxxxx
+ sudot. */
+ return 2395;
}
}
}
@@ -6967,11 +6989,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x0xx0xxxxx011x10xxxxxxxxxx
- sqdmlslb. */
- return 2172;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx0xxxxx011010xxxxxxxxxx
+ sqdmlslb. */
+ return 2172;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx0xxxxx011110xxxxxxxxxx
+ usdot. */
+ return 2393;
+ }
}
}
else
@@ -8674,7 +8707,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0100xxx10101xxxxxxxxxxxxx
bfcvtnt. */
- return 2394;
+ return 2422;
}
}
else
@@ -8806,9 +8839,9 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
@@ -8822,58 +8855,69 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x11001x00100xxxx111xxxxxxxxxxxxx
- st1b. */
- return 1872;
+ x11001x00001xxxx111xxxxxxxxxxxxx
+ stnt1b. */
+ return 1933;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x11001x01100xxxx111xxxxxxxxxxxxx
- st1h. */
- return 1893;
+ x11001x01001xxxx111xxxxxxxxxxxxx
+ stnt1h. */
+ return 1937;
}
}
}
else
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x11001x00001xxxx111xxxxxxxxxxxxx
- stnt1b. */
- return 1933;
+ x11001x00100xxxx111xxxxxxxxxxxxx
+ st1b. */
+ return 1872;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x11001x01001xxxx111xxxxxxxxxxxxx
- stnt1h. */
- return 1937;
+ x11001x00101xxxx111xxxxxxxxxxxxx
+ st3b. */
+ return 1917;
}
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 31) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x11001x00101xxxx111xxxxxxxxxxxxx
- st3b. */
- return 1917;
+ 011001x0110xxxxx111xxxxxxxxxxxxx
+ fmmla. */
+ return 2397;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x11001x01101xxxx111xxxxxxxxxxxxx
- st3h. */
- return 1921;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x01100xxxx111xxxxxxxxxxxxx
+ st1h. */
+ return 1893;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x01101xxxx111xxxxxxxxxxxxx
+ st3h. */
+ return 1921;
+ }
}
}
}
@@ -8909,85 +8953,107 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x0001xxxxx0x0xxxxxxxxxxxxx
- ld1b. */
- return 1501;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x0101xxxxx0x0xxxxxxxxxxxxx
- ld1h. */
- return 1521;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x00x1xxxxxx00xxxxxxxxxxxxx
+ ld1rob. */
+ return 2398;
}
else
{
- if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x0011xxxxx0x0xxxxxxxxxxxxx
- ld1b. */
- return 1503;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x0111xxxxx0x0xxxxxxxxxxxxx
- ld1h. */
- return 1523;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x01x1xxxxxx00xxxxxxxxxxxxx
+ ld1roh. */
+ return 2399;
}
}
else
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x0001xxxxx1x0xxxxxxxxxxxxx
- ld2b. */
- return 1599;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x0001xxxxx010xxxxxxxxxxxxx
+ ld1b. */
+ return 1501;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x0101xxxxx010xxxxxxxxxxxxx
+ ld1h. */
+ return 1521;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x0101xxxxx1x0xxxxxxxxxxxxx
- ld2h. */
- return 1603;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x0011xxxxx010xxxxxxxxxxxxx
+ ld1b. */
+ return 1503;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x0111xxxxx010xxxxxxxxxxxxx
+ ld1h. */
+ return 1523;
+ }
}
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x0011xxxxx1x0xxxxxxxxxxxxx
- ld4b. */
- return 1615;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x0001xxxxx110xxxxxxxxxxxxx
+ ld2b. */
+ return 1599;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x0101xxxxx110xxxxxxxxxxxxx
+ ld2h. */
+ return 1603;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x0111xxxxx1x0xxxxxxxxxxxxx
- ld4h. */
- return 1619;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x0011xxxxx110xxxxxxxxxxxxx
+ ld4b. */
+ return 1615;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x0111xxxxx110xxxxxxxxxxxxx
+ ld4h. */
+ return 1619;
+ }
}
}
}
@@ -9135,7 +9201,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xxxxxxxxxxxxx
bfdot. */
- return 2391;
+ return 2419;
}
else
{
@@ -9156,7 +9222,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx010xx0xxxxxxxxxx
bfmlalb. */
- return 2398;
+ return 2426;
}
else
{
@@ -9164,7 +9230,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx010xx1xxxxxxxxxx
bfmlalt. */
- return 2397;
+ return 2425;
}
}
else
@@ -9219,7 +9285,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx1x0xxxxxxxxxxxxx
bfdot. */
- return 2390;
+ return 2418;
}
else
{
@@ -9231,7 +9297,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx1x0xx0xxxxxxxxxx
bfmlalb. */
- return 2396;
+ return 2424;
}
else
{
@@ -9239,7 +9305,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx1x0xx1xxxxxxxxxx
bfmlalt. */
- return 2395;
+ return 2423;
}
}
else
@@ -9282,85 +9348,107 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 14) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x00010xxxxx01xxxxxxxxxxxxx
- ld1b. */
- return 1508;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x01010xxxxx01xxxxxxxxxxxxx
- ld1h. */
- return 1529;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x00x1xxxxx001xxxxxxxxxxxxx
+ ld1rob. */
+ return 2402;
}
else
{
- if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x00110xxxxx01xxxxxxxxxxxxx
- ld1b. */
- return 1510;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x01110xxxxx01xxxxxxxxxxxxx
- ld1h. */
- return 1531;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x01x1xxxxx001xxxxxxxxxxxxx
+ ld1roh. */
+ return 2403;
}
}
else
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x00011xxxxx01xxxxxxxxxxxxx
- ldnf1b. */
- return 1700;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x00010xxxx101xxxxxxxxxxxxx
+ ld1b. */
+ return 1508;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x01010xxxx101xxxxxxxxxxxxx
+ ld1h. */
+ return 1529;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x01011xxxxx01xxxxxxxxxxxxx
- ldnf1h. */
- return 1704;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x00110xxxx101xxxxxxxxxxxxx
+ ld1b. */
+ return 1510;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x01110xxxx101xxxxxxxxxxxxx
+ ld1h. */
+ return 1531;
+ }
}
}
else
{
- if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x00111xxxxx01xxxxxxxxxxxxx
- ldnf1b. */
- return 1702;
- }
- else
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 101001x01111xxxxx01xxxxxxxxxxxxx
- ldnf1h. */
- return 1706;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x00011xxxx101xxxxxxxxxxxxx
+ ldnf1b. */
+ return 1700;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x01011xxxx101xxxxxxxxxxxxx
+ ldnf1h. */
+ return 1704;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x00111xxxx101xxxxxxxxxxxxx
+ ldnf1b. */
+ return 1702;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x01111xxxx101xxxxxxxxxxxxx
+ ldnf1h. */
+ return 1706;
+ }
}
}
}
@@ -9608,9 +9696,9 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
@@ -9622,28 +9710,39 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x11001x01010xxxx111xxxxxxxxxxxxx
- st1h. */
- return 1891;
+ x11001x00011xxxx111xxxxxxxxxxxxx
+ st2b. */
+ return 1909;
}
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 31) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x11001x00011xxxx111xxxxxxxxxxxxx
- st2b. */
- return 1909;
+ 011001x0101xxxxx111xxxxxxxxxxxxx
+ fmmla. */
+ return 2396;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x11001x01011xxxx111xxxxxxxxxxxxx
- st2h. */
- return 1913;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x01010xxxx111xxxxxxxxxxxxx
+ st1h. */
+ return 1891;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x01011xxxx111xxxxxxxxxxxxx
+ st2h. */
+ return 1913;
+ }
}
}
}
@@ -9657,7 +9756,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx111xxxxxxxxxxxxx
bfmmla. */
- return 2392;
+ return 2420;
}
else
{
@@ -9787,11 +9886,77 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1x01xxxxx000xxxxxxxxxxxxx
- ext. */
- return 1374;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1001xxxxx000xxxxxxxxxxxxx
+ ext. */
+ return 1374;
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1101xxxxx000x00xxxxxxxxxx
+ zip1. */
+ return 2406;
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1101xxxxx000010xxxxxxxxxx
+ uzip1. */
+ return 2408;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1101xxxxx000110xxxxxxxxxx
+ trn1. */
+ return 2410;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1101xxxxx000x01xxxxxxxxxx
+ zip2. */
+ return 2407;
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1101xxxxx000011xxxxxxxxxx
+ uzip2. */
+ return 2409;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1101xxxxx000111xxxxxxxxxx
+ trn2. */
+ return 2411;
+ }
+ }
+ }
+ }
}
else
{
@@ -10817,11 +10982,44 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x1xx0xxxxx100x10xxxxxxxxxx
- ssublbt. */
- return 2233;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1xx0xxxxx100010xxxxxxxxxx
+ ssublbt. */
+ return 2233;
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1000xxxxx100110xxxxxxxxxx
+ smmla. */
+ return 2390;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1100xxxxx100110xxxxxxxxxx
+ usmmla. */
+ return 2392;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1x10xxxxx100110xxxxxxxxxx
+ ummla. */
+ return 2391;
+ }
+ }
}
}
else
@@ -12134,176 +12332,198 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 4) & 0x1) == 0)
- {
- if (((word >> 10) & 0x1) == 0)
- {
- if (((word >> 11) & 0x1) == 0)
- {
- if (((word >> 12) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000000xxxxx0xxxx
- whilege. */
- return 2313;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000100xxxxx0xxxx
- whilege. */
- return 2314;
- }
- }
- else
- {
- if (((word >> 12) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000010xxxxx0xxxx
- whilehs. */
- return 2319;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000110xxxxx0xxxx
- whilehs. */
- return 2320;
- }
- }
- }
- else
- {
- if (((word >> 11) & 0x1) == 0)
- {
- if (((word >> 12) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000001xxxxx0xxxx
- whilelt. */
- return 2025;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000101xxxxx0xxxx
- whilelt. */
- return 2026;
- }
- }
- else
- {
- if (((word >> 12) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000011xxxxx0xxxx
- whilelo. */
- return 2021;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000111xxxxx0xxxx
- whilelo. */
- return 2022;
- }
- }
- }
- }
- else
+ if (((word >> 31) & 0x1) == 0)
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 4) & 0x1) == 0)
{
- if (((word >> 11) & 0x1) == 0)
+ if (((word >> 10) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000000xxxxx1xxxx
- whilegt. */
- return 2315;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000000xxxxx0xxxx
+ whilege. */
+ return 2313;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000100xxxxx0xxxx
+ whilege. */
+ return 2314;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000100xxxxx1xxxx
- whilegt. */
- return 2316;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000010xxxxx0xxxx
+ whilehs. */
+ return 2319;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000110xxxxx0xxxx
+ whilehs. */
+ return 2320;
+ }
}
}
else
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000010xxxxx1xxxx
- whilehi. */
- return 2317;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000001xxxxx0xxxx
+ whilelt. */
+ return 2025;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000101xxxxx0xxxx
+ whilelt. */
+ return 2026;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000110xxxxx1xxxx
- whilehi. */
- return 2318;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000011xxxxx0xxxx
+ whilelo. */
+ return 2021;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000111xxxxx0xxxx
+ whilelo. */
+ return 2022;
+ }
}
}
}
else
{
- if (((word >> 11) & 0x1) == 0)
+ if (((word >> 10) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000001xxxxx1xxxx
- whilele. */
- return 2019;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000000xxxxx1xxxx
+ whilegt. */
+ return 2315;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000100xxxxx1xxxx
+ whilegt. */
+ return 2316;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000101xxxxx1xxxx
- whilele. */
- return 2020;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000010xxxxx1xxxx
+ whilehi. */
+ return 2317;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000110xxxxx1xxxx
+ whilehi. */
+ return 2318;
+ }
}
}
else
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000011xxxxx1xxxx
- whilels. */
- return 2023;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000001xxxxx1xxxx
+ whilele. */
+ return 2019;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000101xxxxx1xxxx
+ whilele. */
+ return 2020;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx000111xxxxx1xxxx
- whilels. */
- return 2024;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000011xxxxx1xxxx
+ whilels. */
+ return 2023;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx000111xxxxx1xxxx
+ whilels. */
+ return 2024;
+ }
}
}
}
}
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x10x1xxxxx000xxxxxxxxxxxxx
+ ld1row. */
+ return 2400;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x11x1xxxxx000xxxxxxxxxxxxx
+ ld1rod. */
+ return 2401;
+ }
+ }
}
}
else
@@ -12626,42 +12846,64 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 30) & 0x1) == 0)
{
- if (((word >> 4) & 0x1) == 0)
+ if (((word >> 31) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 4) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx0010xxxxxxx0xxxx
- ctermeq. */
- return 1353;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx0010xxxxxxx0xxxx
+ ctermeq. */
+ return 1353;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx0011xxxxxxx0xxxx
+ whilewr. */
+ return 2322;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1xx1xxxxx0011xxxxxxx0xxxx
- whilewr. */
- return 2322;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx0010xxxxxxx1xxxx
+ ctermne. */
+ return 1354;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx0011xxxxxxx1xxxx
+ whilerw. */
+ return 2321;
+ }
}
}
else
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x01001x1xx1xxxxx0010xxxxxxx1xxxx
- ctermne. */
- return 1354;
+ 101001x10x1xxxxx001xxxxxxxxxxxxx
+ ld1row. */
+ return 2404;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x01001x1xx1xxxxx0011xxxxxxx1xxxx
- whilerw. */
- return 2321;
+ 101001x11x1xxxxx001xxxxxxxxxxxxx
+ ld1rod. */
+ return 2405;
}
}
}
@@ -14095,7 +14337,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x110001x10101xxxxxxxxxxxxx
bfcvt. */
- return 2393;
+ return 2421;
}
}
else
@@ -16150,11 +16392,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110xx0xxxxxxx1001xxxxxxxxxx
- fcmeq. */
- return 300;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110xx0xxxxx0x1001xxxxxxxxxx
+ fcmeq. */
+ return 300;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110xx0xxxxx1x1001xxxxxxxxxx
+ smmla. */
+ return 2412;
+ }
}
}
else
@@ -16246,32 +16499,54 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110xx0xxxxxxx1011xxxxxxxxxx
- smov. */
- return 151;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110xx0xxxxx0x1011xxxxxxxxxx
+ smov. */
+ return 151;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110xx0xxxxx1x1011xxxxxxxxxx
+ usmmla. */
+ return 2414;
+ }
}
}
else
{
if (((word >> 13) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110x00xxxxxxx0111xxxxxxxxxx
- ins. */
- return 154;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110x00xxxxx0x0111xxxxxxxxxx
+ ins. */
+ return 154;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110x10xxxxx0x0111xxxxxxxxxx
+ fmulx. */
+ return 298;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 0x001110x10xxxxxxx0111xxxxxxxxxx
- fmulx. */
- return 298;
+ 0x001110xx0xxxxx1x0111xxxxxxxxxx
+ usdot. */
+ return 2415;
}
}
else
@@ -16604,11 +16879,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx101110xx0xxxxx1x1x01xxxxxxxxxx
- fcadd. */
- return 373;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx101110xx0xxxxx101x01xxxxxxxxxx
+ ummla. */
+ return 2413;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx101110xx0xxxxx111x01xxxxxxxxxx
+ fcadd. */
+ return 373;
+ }
}
else
{
@@ -16618,7 +16904,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110xx0xxxxx1x1011xxxxxxxxxx
bfmmla. */
- return 2401;
+ return 2429;
}
else
{
@@ -16628,7 +16914,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011100x0xxxxx1x1111xxxxxxxxxx
bfdot. */
- return 2399;
+ return 2427;
}
else
{
@@ -16638,7 +16924,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x01011101x0xxxxx1x1111xxxxxxxxxx
bfmlalb. */
- return 2406;
+ return 2434;
}
else
{
@@ -16646,7 +16932,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11011101x0xxxxx1x1111xxxxxxxxxx
bfmlalt. */
- return 2405;
+ return 2433;
}
}
}
@@ -17230,7 +17516,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000011101x1xxxx1011010xxxxxxxxxx
bfcvtn. */
- return 2402;
+ return 2430;
}
else
{
@@ -17238,7 +17524,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010011101x1xxxx1011010xxxxxxxxxx
bfcvtn2. */
- return 2403;
+ return 2431;
}
}
}
@@ -22332,31 +22618,53 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0011110xxxxxxx1111x0xxxxxxxxxx
- bfdot. */
- return 2400;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx00111100xxxxxx1111x0xxxxxxxxxx
+ sudot. */
+ return 2417;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx00111110xxxxxx1111x0xxxxxxxxxx
+ usdot. */
+ return 2416;
+ }
}
else
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x00011111xxxxxxx1111x0xxxxxxxxxx
- bfmlalb. */
- return 2408;
+ xx00111101xxxxxx1111x0xxxxxxxxxx
+ bfdot. */
+ return 2428;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10011111xxxxxxx1111x0xxxxxxxxxx
- bfmlalt. */
- return 2407;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x000111111xxxxxx1111x0xxxxxxxxxx
+ bfmlalb. */
+ return 2436;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x100111111xxxxxx1111x0xxxxxxxxxx
+ bfmlalt. */
+ return 2435;
+ }
}
}
}
@@ -22985,8 +23293,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
case 823: return NULL; /* fsqrt --> NULL. */
case 831: value = 832; break; /* frintz --> frintz. */
case 832: return NULL; /* frintz --> NULL. */
- case 824: value = 2404; break; /* fcvt --> bfcvt. */
- case 2404: return NULL; /* bfcvt --> NULL. */
+ case 824: value = 2432; break; /* fcvt --> bfcvt. */
+ case 2432: return NULL; /* bfcvt --> NULL. */
case 833: value = 834; break; /* frinta --> frinta. */
case 834: return NULL; /* frinta --> NULL. */
case 835: value = 836; break; /* frintx --> frintx. */
@@ -23460,7 +23768,6 @@ aarch64_extract_operand (const aarch64_operand *self,
case 28:
case 29:
case 30:
- case 162:
case 163:
case 164:
case 165:
@@ -23470,7 +23777,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 169:
case 170:
case 171:
- case 186:
+ case 172:
case 187:
case 188:
case 189:
@@ -23479,8 +23786,9 @@ aarch64_extract_operand (const aarch64_operand *self,
case 192:
case 193:
case 194:
- case 200:
- case 203:
+ case 195:
+ case 201:
+ case 204:
return aarch64_ext_regno (self, info, code, inst, errors);
case 9:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -23496,7 +23804,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 32:
case 33:
case 34:
- case 206:
+ case 207:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 35:
return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -23531,9 +23839,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 80:
case 81:
case 82:
- case 159:
- case 161:
- case 178:
+ case 160:
+ case 162:
case 179:
case 180:
case 181:
@@ -23541,7 +23848,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 183:
case 184:
case 185:
- case 205:
+ case 186:
+ case 206:
return aarch64_ext_imm (self, info, code, inst, errors);
case 43:
case 44:
@@ -23553,10 +23861,10 @@ aarch64_extract_operand (const aarch64_operand *self,
case 48:
return aarch64_ext_shll_imm (self, info, code, inst, errors);
case 51:
- case 149:
+ case 150:
return aarch64_ext_fpimm (self, info, code, inst, errors);
case 68:
- case 157:
+ case 158:
return aarch64_ext_limm (self, info, code, inst, errors);
case 69:
return aarch64_ext_aimm (self, info, code, inst, errors);
@@ -23566,11 +23874,11 @@ aarch64_extract_operand (const aarch64_operand *self,
return aarch64_ext_fbits (self, info, code, inst, errors);
case 73:
case 74:
- case 154:
+ case 155:
return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
case 75:
- case 153:
- case 155:
+ case 154:
+ case 156:
return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
case 76:
case 77:
@@ -23613,22 +23921,22 @@ aarch64_extract_operand (const aarch64_operand *self,
case 106:
return aarch64_ext_hint (self, info, code, inst, errors);
case 107:
- return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors);
case 108:
+ return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors);
case 109:
case 110:
case 111:
- return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 112:
- return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 113:
- return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 114:
+ return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 115:
case 116:
case 117:
- return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors);
case 118:
+ return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors);
case 119:
case 120:
case 121:
@@ -23642,8 +23950,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 129:
case 130:
case 131:
- return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
case 132:
+ return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
case 133:
case 134:
case 135:
@@ -23651,52 +23959,53 @@ aarch64_extract_operand (const aarch64_operand *self,
case 137:
case 138:
case 139:
- return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
case 140:
+ return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
case 141:
case 142:
case 143:
- return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
case 144:
- return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
case 145:
- return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
case 146:
- return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 147:
- return aarch64_ext_sve_aimm (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 148:
+ return aarch64_ext_sve_aimm (self, info, code, inst, errors);
+ case 149:
return aarch64_ext_sve_asimm (self, info, code, inst, errors);
- case 150:
- return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
case 151:
- return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
+ return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
case 152:
+ return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
+ case 153:
return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
- case 156:
+ case 157:
return aarch64_ext_inv_limm (self, info, code, inst, errors);
- case 158:
+ case 159:
return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
- case 160:
+ case 161:
return aarch64_ext_sve_scale (self, info, code, inst, errors);
- case 172:
case 173:
case 174:
- return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 175:
+ return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 176:
case 177:
+ case 178:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
- case 195:
case 196:
case 197:
case 198:
case 199:
+ case 200:
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
- case 201:
- return aarch64_ext_sve_index (self, info, code, inst, errors);
case 202:
- case 204:
+ return aarch64_ext_sve_index (self, info, code, inst, errors);
+ case 203:
+ case 205:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 178d2108d7a7c6b1401e890de73722f60baf4746..a1b789bebf1326d3d94c8d9b14b7e9934b6d19db 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -132,6 +132,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB option name CSYNC"},
{AARCH64_OPND_CLASS_SYSTEM, "BTI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "BTI targets j/c/jc"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16"},
+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x32", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 32"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by VL"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 2*VL"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x3xVL", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 3*VL"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index d8e0e4b0634bff0e77c48453eeeb0f49d173b8fe..086f2419a875c42b33cd24c2b88df4f028aecc57 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1899,6 +1899,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
break;
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
+ case AARCH64_OPND_SVE_ADDR_RI_S4x32:
min_value = -8;
max_value = 7;
goto sve_imm_offset;
@@ -3639,6 +3640,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_ADDR_SIMM13:
case AARCH64_OPND_ADDR_OFFSET:
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
+ case AARCH64_OPND_SVE_ADDR_RI_S4x32:
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index ced511a9b8477f6ee6a17edc9ce3817930376e6d..5305c0c63cdacb91dce1bb4b7af7cf07fff587f7 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1519,6 +1519,10 @@
{ \
QLF3(S_D,S_D,S_D), \
}
+#define OP_SVE_QQQ \
+{ \
+ QLF3(S_Q,S_Q,S_Q), \
+}
#define OP_SVE_DDDD \
{ \
QLF4(S_D,S_D,S_D,S_D), \
@@ -1663,6 +1667,10 @@
{ \
QLF3(S_S,P_Z,S_S), \
}
+#define OP_SVE_SBB \
+{ \
+ QLF3(S_S,S_B,S_B), \
+}
#define OP_SVE_SBBU \
{ \
QLF4(S_S,S_B,S_B,NIL), \
@@ -2272,6 +2280,12 @@
QLF3(V_4S, V_8H, S_2H),\
}
+/* e.g. SMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B */
+#define QL_MMLA64 \
+{ \
+ QLF3(V_4S, V_16B, V_16B),\
+}
+
/* e.g. BFMMLA <Vd>.4s, <Vn>.8h, <Vm>.8h */
#define QL_BFMMLA \
{ \
@@ -2393,6 +2407,17 @@ static const aarch64_feature_set aarch64_feature_sve2bitperm =
AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0);
static const aarch64_feature_set aarch64_feature_v8_6 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0);
+static const aarch64_feature_set aarch64_feature_i8mm =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_I8MM, 0);
+static const aarch64_feature_set aarch64_feature_i8mm_sve =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_I8MM
+ | AARCH64_FEATURE_SVE, 0);
+static const aarch64_feature_set aarch64_feature_f32mm_sve =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F32MM
+ | AARCH64_FEATURE_SVE, 0);
+static const aarch64_feature_set aarch64_feature_f64mm_sve =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F64MM
+ | AARCH64_FEATURE_SVE, 0);
#define CORE &aarch64_feature_v8
@@ -2435,8 +2460,13 @@ static const aarch64_feature_set aarch64_feature_v8_6 =
#define SVE2_SM4 &aarch64_feature_sve2sm4
#define SVE2_BITPERM &aarch64_feature_sve2bitperm
#define ARMV8_6 &aarch64_feature_v8_6
+#define ARMV8_6_SVE &aarch64_feature_v8_6
#define BFLOAT16_SVE &aarch64_feature_bfloat16_sve
#define BFLOAT16 &aarch64_feature_bfloat16
+#define I8MM_SVE &aarch64_feature_i8mm_sve
+#define F32MM_SVE &aarch64_feature_f32mm_sve
+#define F64MM_SVE &aarch64_feature_f64mm_sve
+#define I8MM &aarch64_feature_i8mm
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2534,6 +2564,16 @@ static const aarch64_feature_set aarch64_feature_v8_6 =
CONSTRAINTS, TIED, NULL }
#define BFLOAT16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, BFLOAT16, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define INT8MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \
+ { NAME, OPCODE, MASK, CLASS, 0, I8MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
+#define INT8MATMUL_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, I8MM, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define F64MATMUL_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, 0, TIED, NULL }
+#define F64MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \
+ { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
+#define F32MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \
+ { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
struct aarch64_opcode aarch64_opcode_table[] =
{
@@ -5032,6 +5072,37 @@ struct aarch64_opcode aarch64_opcode_table[] =
V8_4_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
V8_4_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
+ /* Matrix Multiply instructions. */
+ INT8MATMUL_SVE_INSNC ("smmla", 0x45009800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
+ INT8MATMUL_SVE_INSNC ("ummla", 0x45c09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
+ INT8MATMUL_SVE_INSNC ("usmmla", 0x45809800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
+ INT8MATMUL_SVE_INSNC ("usdot", 0x44807800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
+ INT8MATMUL_SVE_INSNC ("usdot", 0x44a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
+ INT8MATMUL_SVE_INSNC ("sudot", 0x44a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
+ F32MATMUL_SVE_INSNC ("fmmla", 0x64a0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0),
+ F64MATMUL_SVE_INSNC ("fmmla", 0x64c0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0),
+ F64MATMUL_SVE_INSN ("ld1rob", 0xa4200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0),
+ F64MATMUL_SVE_INSN ("ld1roh", 0xa4a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HZU, F_OD(1), 0),
+ F64MATMUL_SVE_INSN ("ld1row", 0xa5200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SZU, F_OD(1), 0),
+ F64MATMUL_SVE_INSN ("ld1rod", 0xa5a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_DZU, F_OD(1), 0),
+ F64MATMUL_SVE_INSN ("ld1rob", 0xa4202000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_BZU, F_OD(1), 0),
+ F64MATMUL_SVE_INSN ("ld1roh", 0xa4a02000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_HZU, F_OD(1), 0),
+ F64MATMUL_SVE_INSN ("ld1row", 0xa5202000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_SZU, F_OD(1), 0),
+ F64MATMUL_SVE_INSN ("ld1rod", 0xa5a02000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_DZU, F_OD(1), 0),
+ F64MATMUL_SVE_INSN ("zip1", 0x05a00000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
+ F64MATMUL_SVE_INSN ("zip2", 0x05a00400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
+ F64MATMUL_SVE_INSN ("uzip1", 0x05a00800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
+ F64MATMUL_SVE_INSN ("uzip2", 0x05a00c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
+ F64MATMUL_SVE_INSN ("trn1", 0x05a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
+ F64MATMUL_SVE_INSN ("trn2", 0x05a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
+ /* Matrix Multiply advanced SIMD instructions. */
+ INT8MATMUL_INSN ("smmla", 0x4e80a400, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_MMLA64, 0),
+ INT8MATMUL_INSN ("ummla", 0x6e80a400, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_MMLA64, 0),
+ INT8MATMUL_INSN ("usmmla", 0x4e80ac00, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_MMLA64, 0),
+ INT8MATMUL_INSN ("usdot", 0x4e809c00, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
+ INT8MATMUL_INSN ("usdot", 0x4f80f000, 0xffc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
+ INT8MATMUL_INSN ("sudot", 0x4f00f000, 0xffc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
+
/* BFloat instructions. */
BFLOAT16_SVE_INSNC ("bfdot", 0x64608000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
BFLOAT16_SVE_INSNC ("bfdot", 0x64604000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
@@ -5263,6 +5334,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \
4 << OPD_F_OD_LSB, F(FLD_Rn), \
"an address with a 4-bit signed offset, multiplied by 16") \
+ Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x32", \
+ 5 << OPD_F_OD_LSB, F(FLD_Rn), \
+ "an address with a 4-bit signed offset, multiplied by 32") \
Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4xVL", \
0 << OPD_F_OD_LSB, F(FLD_Rn), \
"an address with a 4-bit signed offset, multiplied by VL") \