[PATCH] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.

[Nelson Chu]

Dear binutils,

According to the riscv privilege spec, some CSR are only valid when
rv32 or the specific extension is set.  The current toolchain doesn't
have enough information to let assembler know which CSR is valid.
Therefore, we use `riscv_csrs` table, just like `riscv_opcode`, to
record all the information we need, and then check whether the CSR is
valid according to these information.

This patch only support the RV32 and f-ext checking currently.  If we
want to implement more checking for CSR, then we just need to extend
the `riscv_csrs` table, and do some corresponding modifications in
gas/conifg/tc-riscv.c.  I also update all the CSR to the current
privilege spec (1.12), and upadte all the CSR testsuites.

The spec version checking may be supported in the future patch if
needed.  As for the privilege mode and the read/write access checking,
It is not necessary to record these information in the `riscv_csrs`
table , since we can get these information from the top 4-bits [11:8]
of CSR address.

* Check [11:10] bits and then get the read and write access:
00, 01, 10 -> Read/Write
11 -> Read only

* Check [9:8] bits and then get the privilege mode:
00 -> User-level
01 -> Supervisor-level
10 -> Hyper-vision level
11 -> Machine-level

Thanks
Best Regards
Nelson
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