[PATCH] x86: Add support for Intel ENQCMD[S] instructions
Cui, Lili
lili.cui@intel.com
Fri May 31 06:57:00 GMT 2019
Hi all,
This patch is about to enable support for ENQCMD[S] in binutils. which will be in Willow Cove.
About ENQCMD[S] details please refer to
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Make check-gas is ok.
gas/ChangeLog:
2019-05-28 Xuepeng Guo <xuepeng.guo@intel.com>
Lili Cui <lili.cui@intel.com>
* doc/c-i386.texi: Document enqcmd.
* testsuite/gas/i386/enqcmd-intel.d: New file.
* testsuite/gas/i386/enqcmd-inval.l: Likewise.
* testsuite/gas/i386/enqcmd-inval.s: Likewise.
* testsuite/gas/i386/enqcmd.d: Likewise.
* testsuite/gas/i386/enqcmd.s: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
* testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
and x86-64-enqcmd.
opcodes/ChangeLog:
2019-05-28 Xuepeng Guo <xuepeng.guo@intel.com>
Lili Cui <lili.cui@intel.com>
* i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and
MOD_0F38F8_PREFIX_3.
(prefix_table): New instructions (see prefix above).
(mod_table): New instructions (see prefix above).
* i386-gen.c (cpu_flag_init): Add entries for enqcmd.
(cpu_flags): Add a bitfield for enqmcd.
* i386-init.h: Regenerated.
* i386-opc.h (enum): Add CpuENQCMD.
(i386_cpu_flags): Add a bitfield for cpuenqcmd.
* i386-opc.tbl: Add enqcmd and enqcmds instructions.
* i386-tbl.h: Regenerated.
---
gas/doc/c-i386.texi | 3 ++-
gas/testsuite/gas/i386/enqcmd-intel.d | 20 ++++++++++++++++++++
gas/testsuite/gas/i386/enqcmd-inval.l | 10 ++++++++++
gas/testsuite/gas/i386/enqcmd-inval.s | 15 +++++++++++++++
gas/testsuite/gas/i386/enqcmd.d | 20 ++++++++++++++++++++
gas/testsuite/gas/i386/enqcmd.s | 15 +++++++++++++++
gas/testsuite/gas/i386/i386.exp | 6 ++++++
gas/testsuite/gas/i386/x86-64-enqcmd-intel.d | 20 ++++++++++++++++++++
gas/testsuite/gas/i386/x86-64-enqcmd-inval.l | 9 +++++++++
gas/testsuite/gas/i386/x86-64-enqcmd-inval.s | 15 +++++++++++++++
gas/testsuite/gas/i386/x86-64-enqcmd.d | 20 ++++++++++++++++++++
gas/testsuite/gas/i386/x86-64-enqcmd.s | 15 +++++++++++++++
opcodes/i386-dis.c | 13 ++++++++++++-
opcodes/i386-gen.c | 5 +++++
opcodes/i386-opc.h | 3 +++
opcodes/i386-opc.tbl | 9 +++++++++
16 files changed, 196 insertions(+), 2 deletions(-)
create mode 100644 gas/testsuite/gas/i386/enqcmd-intel.d
create mode 100644 gas/testsuite/gas/i386/enqcmd-inval.l
create mode 100644 gas/testsuite/gas/i386/enqcmd-inval.s
create mode 100644 gas/testsuite/gas/i386/enqcmd.d
create mode 100644 gas/testsuite/gas/i386/enqcmd.s
create mode 100644 gas/testsuite/gas/i386/x86-64-enqcmd-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-enqcmd-inval.l
create mode 100644 gas/testsuite/gas/i386/x86-64-enqcmd-inval.s
create mode 100644 gas/testsuite/gas/i386/x86-64-enqcmd.d
create mode 100644 gas/testsuite/gas/i386/x86-64-enqcmd.s
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 86cde7907e..77e6684afc 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -183,6 +183,7 @@ accept various extension mnemonics. For example,
@code{clwb},
@code{movdiri},
@code{movdir64b},
+@code{enqcmd},
@code{avx512f},
@code{avx512cd},
@code{avx512er},
@@ -1309,7 +1310,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
-@item @samp{.movdiri} @tab @samp{.movdir64b}
+@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
diff --git a/gas/testsuite/gas/i386/enqcmd-intel.d b/gas/testsuite/gas/i386/enqcmd-intel.d
new file mode 100644
index 0000000000..b38c3ed6ee
--- /dev/null
+++ b/gas/testsuite/gas/i386/enqcmd-intel.d
@@ -0,0 +1,20 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 ENQCMD[S] insns (Intel disassembly)
+#source: enqcmd.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*f2 0f 38 f8 01[ ]*enqcmd eax,\[ecx\]
+[ ]*[a-f0-9]+:[ ]*67 f2 0f 38 f8 04[ ]*enqcmd ax,\[si\]
+[ ]*[a-f0-9]+:[ ]*f3 0f 38 f8 01[ ]*enqcmds eax,\[ecx\]
+[ ]*[a-f0-9]+:[ ]*67 f3 0f 38 f8 04[ ]*enqcmds ax,\[si\]
+[ ]*[a-f0-9]+:[ ]*f2 0f 38 f8 01[ ]*enqcmd eax,\[ecx\]
+[ ]*[a-f0-9]+:[ ]*67 f2 0f 38 f8 04[ ]*enqcmd ax,\[si\]
+[ ]*[a-f0-9]+:[ ]*f3 0f 38 f8 01[ ]*enqcmds eax,\[ecx\]
+[ ]*[a-f0-9]+:[ ]*67 f3 0f 38 f8 04[ ]*enqcmds ax,\[si\]
+#pass
diff --git a/gas/testsuite/gas/i386/enqcmd-inval.l b/gas/testsuite/gas/i386/enqcmd-inval.l
new file mode 100644
index 0000000000..e5af4c796e
--- /dev/null
+++ b/gas/testsuite/gas/i386/enqcmd-inval.l
@@ -0,0 +1,10 @@
+.*: Assembler messages:
+.*:6: Error: invalid register operand size for `enqcmd'
+.*:7: Error: invalid register operand size for `enqcmd'
+.*:8: Error: invalid register operand size for `enqcmds'
+.*:9: Error: invalid register operand size for `enqcmds'
+.*:12: Error: invalid register operand size for `enqcmd'
+.*:13: Error: invalid register operand size for `enqcmd'
+.*:14: Error: invalid register operand size for `enqcmds'
+.*:15: Error: invalid register operand size for `enqcmds'
+
diff --git a/gas/testsuite/gas/i386/enqcmd-inval.s b/gas/testsuite/gas/i386/enqcmd-inval.s
new file mode 100644
index 0000000000..33eb6c8c3e
--- /dev/null
+++ b/gas/testsuite/gas/i386/enqcmd-inval.s
@@ -0,0 +1,15 @@
+# Check error for ENQCMD[S] 32-bit instructions
+
+ .allow_index_reg
+ .text
+_start:
+ enqcmd (%si),%eax
+ enqcmd (%esi),%ax
+ enqcmds (%si),%eax
+ enqcmds (%esi),%ax
+
+ .intel_syntax noprefix
+ enqcmd eax,[si]
+ enqcmd ax,[esi]
+ enqcmds eax,[si]
+ enqcmds ax,[esi]
diff --git a/gas/testsuite/gas/i386/enqcmd.d b/gas/testsuite/gas/i386/enqcmd.d
new file mode 100644
index 0000000000..c601185ba3
--- /dev/null
+++ b/gas/testsuite/gas/i386/enqcmd.d
@@ -0,0 +1,20 @@
+#as:
+#objdump: -dw
+#name: i386 ENQCMD[S] insns
+#source: enqcmd.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*f2 0f 38 f8 01[ ]*enqcmd \(%ecx\),%eax
+[ ]*[a-f0-9]+:[ ]*67 f2 0f 38 f8 04[ ]*enqcmd \(%si\),%ax
+[ ]*[a-f0-9]+:[ ]*f3 0f 38 f8 01[ ]*enqcmds \(%ecx\),%eax
+[ ]*[a-f0-9]+:[ ]*67 f3 0f 38 f8 04[ ]*enqcmds \(%si\),%ax
+[ ]*[a-f0-9]+:[ ]*f2 0f 38 f8 01[ ]*enqcmd \(%ecx\),%eax
+[ ]*[a-f0-9]+:[ ]*67 f2 0f 38 f8 04[ ]*enqcmd \(%si\),%ax
+[ ]*[a-f0-9]+:[ ]*f3 0f 38 f8 01[ ]*enqcmds \(%ecx\),%eax
+[ ]*[a-f0-9]+:[ ]*67 f3 0f 38 f8 04[ ]*enqcmds \(%si\),%ax
+#pass
diff --git a/gas/testsuite/gas/i386/enqcmd.s b/gas/testsuite/gas/i386/enqcmd.s
new file mode 100644
index 0000000000..0a23b25a6f
--- /dev/null
+++ b/gas/testsuite/gas/i386/enqcmd.s
@@ -0,0 +1,15 @@
+# Check ENQCMD[S] 32-bit instructions
+
+ .allow_index_reg
+ .text
+_start:
+ enqcmd (%ecx),%eax
+ enqcmd (%si),%ax
+ enqcmds (%ecx),%eax
+ enqcmds (%si),%ax
+
+ .intel_syntax noprefix
+ enqcmd eax,[ecx]
+ enqcmd ax,[si]
+ enqcmds eax,[ecx]
+ enqcmds ax,[si]
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index aa0ad7dc4b..359dfdc350 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -453,6 +453,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "movdir"
run_dump_test "movdir-intel"
run_list_test "movdir64b-reg"
+ run_dump_test "enqcmd"
+ run_dump_test "enqcmd-intel"
+ run_list_test "enqcmd-inval"
run_list_test "avx512vl-1" "-al"
run_list_test "avx512vl-2" "-al"
run_list_test "avx512vl-plain" "-al"
@@ -969,6 +972,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-movdir"
run_dump_test "x86-64-movdir-intel"
run_list_test "x86-64-movdir64b-reg"
+ run_dump_test "x86-64-enqcmd"
+ run_dump_test "x86-64-enqcmd-intel"
+ run_list_test "x86-64-enqcmd-inval"
run_dump_test "x86-64-fence-as-lock-add-yes"
run_dump_test "x86-64-fence-as-lock-add-no"
run_dump_test "x86-64-pr20141"
diff --git a/gas/testsuite/gas/i386/x86-64-enqcmd-intel.d b/gas/testsuite/gas/i386/x86-64-enqcmd-intel.d
new file mode 100644
index 0000000000..e483d570b9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-enqcmd-intel.d
@@ -0,0 +1,20 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 ENQCMD[S] insns (Intel disassembly)
+#source: x86-64-enqcmd.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*f2 0f 38 f8 01[ ]*enqcmd rax,\[rcx\]
+[ ]*[a-f0-9]+:[ ]*67 f2 0f 38 f8 01[ ]*enqcmd eax,\[ecx\]
+[ ]*[a-f0-9]+:[ ]*f3 0f 38 f8 01[ ]*enqcmds rax,\[rcx\]
+[ ]*[a-f0-9]+:[ ]*67 f3 0f 38 f8 01[ ]*enqcmds eax,\[ecx\]
+[ ]*[a-f0-9]+:[ ]*f2 0f 38 f8 01[ ]*enqcmd rax,\[rcx\]
+[ ]*[a-f0-9]+:[ ]*67 f2 0f 38 f8 01[ ]*enqcmd eax,\[ecx\]
+[ ]*[a-f0-9]+:[ ]*f3 0f 38 f8 01[ ]*enqcmds rax,\[rcx\]
+[ ]*[a-f0-9]+:[ ]*67 f3 0f 38 f8 01[ ]*enqcmds eax,\[ecx\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-enqcmd-inval.l b/gas/testsuite/gas/i386/x86-64-enqcmd-inval.l
new file mode 100644
index 0000000000..6b7b6716ff
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-enqcmd-inval.l
@@ -0,0 +1,9 @@
+.* Assembler messages:
+.*6: Error: invalid register operand size for `enqcmd'
+.*7: Error: invalid register operand size for `enqcmd'
+.*8: Error: invalid register operand size for `enqcmds'
+.*9: Error: invalid register operand size for `enqcmds'
+.*12: Error: invalid register operand size for `enqcmd'
+.*13: Error: invalid register operand size for `enqcmd'
+.*14: Error: invalid register operand size for `enqcmds'
+.*15: Error: invalid register operand size for `enqcmds'
diff --git a/gas/testsuite/gas/i386/x86-64-enqcmd-inval.s b/gas/testsuite/gas/i386/x86-64-enqcmd-inval.s
new file mode 100644
index 0000000000..2055c4d99f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-enqcmd-inval.s
@@ -0,0 +1,15 @@
+# Check error for ENQCMD[S] 32-bit instructions
+
+ .allow_index_reg
+ .text
+_start:
+ enqcmd (%esi),%rax
+ enqcmd (%rsi),%eax
+ enqcmds (%esi),%rax
+ enqcmds (%rsi),%eax
+
+ .intel_syntax noprefix
+ enqcmd rax,[esi]
+ enqcmd eax,[rsi]
+ enqcmds rax,[esi]
+ enqcmds eax,[rsi]
diff --git a/gas/testsuite/gas/i386/x86-64-enqcmd.d b/gas/testsuite/gas/i386/x86-64-enqcmd.d
new file mode 100644
index 0000000000..337febf320
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-enqcmd.d
@@ -0,0 +1,20 @@
+#as:
+#objdump: -dw
+#name: x86_64 ENQCMD[S] insns
+#source: x86-64-enqcmd.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*f2 0f 38 f8 01[ ]*enqcmd \(%rcx\),%rax
+[ ]*[a-f0-9]+:[ ]*67 f2 0f 38 f8 01[ ]*enqcmd \(%ecx\),%eax
+[ ]*[a-f0-9]+:[ ]*f3 0f 38 f8 01[ ]*enqcmds \(%rcx\),%rax
+[ ]*[a-f0-9]+:[ ]*67 f3 0f 38 f8 01[ ]*enqcmds \(%ecx\),%eax
+[ ]*[a-f0-9]+:[ ]*f2 0f 38 f8 01[ ]*enqcmd \(%rcx\),%rax
+[ ]*[a-f0-9]+:[ ]*67 f2 0f 38 f8 01[ ]*enqcmd \(%ecx\),%eax
+[ ]*[a-f0-9]+:[ ]*f3 0f 38 f8 01[ ]*enqcmds \(%rcx\),%rax
+[ ]*[a-f0-9]+:[ ]*67 f3 0f 38 f8 01[ ]*enqcmds \(%ecx\),%eax
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-enqcmd.s b/gas/testsuite/gas/i386/x86-64-enqcmd.s
new file mode 100644
index 0000000000..f790b28fc2
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-enqcmd.s
@@ -0,0 +1,15 @@
+# Check ENQCMD[S] 64-bit instructions
+
+ .allow_index_reg
+ .text
+_start:
+ enqcmd (%rcx),%rax
+ enqcmd (%ecx),%eax
+ enqcmds (%rcx),%rax
+ enqcmds (%ecx),%eax
+
+ .intel_syntax noprefix
+ enqcmd rax,[rcx]
+ enqcmd eax,[ecx]
+ enqcmds rax,[rcx]
+ enqcmds eax,[ecx]
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 1ba7b4f2a3..a90f7b462d 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -845,7 +845,9 @@ enum
MOD_0F382A_PREFIX_2,
MOD_0F38F5_PREFIX_2,
MOD_0F38F6_PREFIX_0,
+ MOD_0F38F8_PREFIX_1,
MOD_0F38F8_PREFIX_2,
+ MOD_0F38F8_PREFIX_3,
MOD_0F38F9_PREFIX_0,
MOD_62_32BIT,
MOD_C4_32BIT,
@@ -4444,8 +4446,9 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_0F38F8 */
{
{ Bad_Opcode },
- { Bad_Opcode },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
{ MOD_TABLE (MOD_0F38F8_PREFIX_2) },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
},
/* PREFIX_0F38F9 */
@@ -10519,10 +10522,18 @@ static const struct dis386 mod_table[][2] = {
/* MOD_0F38F6_PREFIX_0 */
{ "wrssK", { M, Gdq }, PREFIX_OPCODE },
},
+ {
+ /* MOD_0F38F8_PREFIX_1 */
+ { "enqcmds", { Gva, M }, PREFIX_OPCODE },
+ },
{
/* MOD_0F38F8_PREFIX_2 */
{ "movdir64b", { Gva, M }, PREFIX_OPCODE },
},
+ {
+ /* MOD_0F38F8_PREFIX_3 */
+ { "enqcmd", { Gva, M }, PREFIX_OPCODE },
+ },
{
/* MOD_0F38F9_PREFIX_0 */
{ "movdiri", { Em, Gv }, PREFIX_OPCODE },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 847a7bb1d9..2f47de64b8 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -295,6 +295,8 @@ static initializer cpu_flag_init[] =
"CpuMOVDIRI" },
{ "CPU_MOVDIR64B_FLAGS",
"CpuMOVDIR64B" },
+ { "CPU_ENQCMD_FLAGS",
+ "CpuENQCMD" },
{ "CPU_ANY_X87_FLAGS",
"CPU_ANY_287_FLAGS|Cpu8087" },
{ "CPU_ANY_287_FLAGS",
@@ -365,6 +367,8 @@ static initializer cpu_flag_init[] =
"CpuMOVDIRI" },
{ "CPU_ANY_MOVDIR64B_FLAGS",
"CpuMOVDIR64B" },
+ { "CPU_ANY_ENQCMD_FLAGS",
+ "CpuENQCMD" },
};
static const initializer operand_type_shorthands[] =
@@ -599,6 +603,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuCLDEMOTE),
BITFIELD (CpuMOVDIRI),
BITFIELD (CpuMOVDIR64B),
+ BITFIELD (CpuENQCMD),
#ifdef CpuUnused
BITFIELD (CpuUnused),
#endif
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 258a218d87..ebf446f42d 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -239,6 +239,8 @@ enum
CpuMOVDIRI,
/* MOVDIRR64B instruction required */
CpuMOVDIR64B,
+ /* ENQCMD instruction required */
+ CpuENQCMD,
/* 64bit support required */
Cpu64,
/* Not supported in the 64bit mode */
@@ -366,6 +368,7 @@ typedef union i386_cpu_flags
unsigned int cpucldemote:1;
unsigned int cpumovdiri:1;
unsigned int cpumovdir64b:1;
+ unsigned int cpuenqcmd:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index f3b3a95d9a..402b982e9e 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -4725,3 +4725,12 @@ vcvtneps2bf16y, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|
vdpbf16ps, 3, 0xf352, None, 1, CpuAVX512_BF16, Modrm|VexOpcode|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
// AVX512_BF16 instructions end.
+
+// ENQCMD instructions.
+
+enqcmd, 2, 0xf20f38f8, None, 3, CpuENQCMD|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOpReg, { Unspecified|BaseIndex, Reg16|Reg32 }
+enqcmd, 2, 0xf20f38f8, None, 3, CpuENQCMD|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|AddrPrefixOpReg, { Unspecified|BaseIndex, Reg32|Reg64 }
+enqcmds, 2, 0xf30f38f8, None, 3, CpuENQCMD|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOpReg, { Unspecified|BaseIndex, Reg16|Reg32 }
+enqcmds, 2, 0xf30f38f8, None, 3, CpuENQCMD|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|AddrPrefixOpReg, { Unspecified|BaseIndex, Reg32|Reg64 }
+
+// ENQCMD instructions end.
--
2.17.1
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