PowerPC reloc symbols that shouldn't be adjusted

[Alan Modra]

GOT and PLT relocs shouldn't have their symbols replaced with a
section symbol plus added.  Nor should the HIGHA TLS relocations,
which failed to be caught by the range test in ppc_fix_adjustable.

bfd/
	* reloc.c (BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA),
	(BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA):
	Sort before BFD_RELOC_PPC64_DTPREL16_HIGHESTA entry.
gas/
	* config/tc-ppc.c (ppc_fix_adjustable): Exclude all GOT and PLT
	relocs, and VLE sdarel relocs.
	* testsuite/gas/ppc/power4.d: Adjust.

diff --git a/bfd/reloc.c b/bfd/reloc.c
index 9615279833..f1465813f7 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -2945,6 +2945,10 @@ ENUMX
   BFD_RELOC_PPC64_TPREL16_DS
 ENUMX
   BFD_RELOC_PPC64_TPREL16_LO_DS
+ENUMX
+  BFD_RELOC_PPC64_TPREL16_HIGH
+ENUMX
+  BFD_RELOC_PPC64_TPREL16_HIGHA
 ENUMX
   BFD_RELOC_PPC64_TPREL16_HIGHER
 ENUMX
@@ -2957,6 +2961,10 @@ ENUMX
   BFD_RELOC_PPC64_DTPREL16_DS
 ENUMX
   BFD_RELOC_PPC64_DTPREL16_LO_DS
+ENUMX
+  BFD_RELOC_PPC64_DTPREL16_HIGH
+ENUMX
+  BFD_RELOC_PPC64_DTPREL16_HIGHA
 ENUMX
   BFD_RELOC_PPC64_DTPREL16_HIGHER
 ENUMX
@@ -2965,14 +2973,6 @@ ENUMX
   BFD_RELOC_PPC64_DTPREL16_HIGHEST
 ENUMX
   BFD_RELOC_PPC64_DTPREL16_HIGHESTA
-ENUMX
-  BFD_RELOC_PPC64_TPREL16_HIGH
-ENUMX
-  BFD_RELOC_PPC64_TPREL16_HIGHA
-ENUMX
-  BFD_RELOC_PPC64_DTPREL16_HIGH
-ENUMX
-  BFD_RELOC_PPC64_DTPREL16_HIGHA
 ENUMDOC
   PowerPC and PowerPC64 thread-local storage relocations.
 
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index c71fe94294..d5d51f78f3 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -6765,7 +6765,27 @@ ppc_fix_adjustable (fixS *fix)
 	  && fix->fx_r_type != BFD_RELOC_HI16_S_GOTOFF
 	  && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_DS
 	  && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_LO_DS
+	  && fix->fx_r_type != BFD_RELOC_16_GOT_PCREL
+	  && fix->fx_r_type != BFD_RELOC_32_GOTOFF
+	  && fix->fx_r_type != BFD_RELOC_24_PLT_PCREL
+	  && fix->fx_r_type != BFD_RELOC_32_PLTOFF
+	  && fix->fx_r_type != BFD_RELOC_32_PLT_PCREL
+	  && fix->fx_r_type != BFD_RELOC_LO16_PLTOFF
+	  && fix->fx_r_type != BFD_RELOC_HI16_PLTOFF
+	  && fix->fx_r_type != BFD_RELOC_HI16_S_PLTOFF
+	  && fix->fx_r_type != BFD_RELOC_64_PLTOFF
+	  && fix->fx_r_type != BFD_RELOC_64_PLT_PCREL
+	  && fix->fx_r_type != BFD_RELOC_PPC64_PLT16_LO_DS
+	  && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16
+	  && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO
+	  && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HI
+	  && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HA
+	  && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_DS
+	  && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO_DS
 	  && fix->fx_r_type != BFD_RELOC_GPREL16
+	  && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_LO16A
+	  && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HI16A
+	  && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HA16A
 	  && fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT
 	  && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY
 	  && !(fix->fx_r_type >= BFD_RELOC_PPC_TLS
diff --git a/gas/testsuite/gas/ppc/power4.d b/gas/testsuite/gas/ppc/power4.d
index cb487a7d02..d3e78a6df1 100644
--- a/gas/testsuite/gas/ppc/power4.d
+++ b/gas/testsuite/gas/ppc/power4.d
@@ -57,7 +57,7 @@ Disassembly of section \.text:
 .*:	(e0 c3 00 00|00 00 c3 e0) 	lq      r6,0\(r3\)
 .*: R_PPC64_GOT16_LO_DS	dsym0
 .*:	(e0 c3 00 00|00 00 c3 e0) 	lq      r6,0\(r3\)
-.*: R_PPC64_PLT16_LO_DS	\.data
+.*: R_PPC64_PLT16_LO_DS	dsym0
 .*:	(e0 c3 00 .0|.0 00 c3 e0) 	lq      r6,.*\(r3\)
 .*: R_PPC64_SECTOFF_DS	\.data\+0x10
 .*:	(e0 c3 00 .0|.0 00 c3 e0) 	lq      r6,.*\(r3\)

-- 
Alan Modra
Australia Development Lab, IBM