[PATCH 13/16] [binutils][aarch64] New sve_size_tsz_bhs iclass.

[Matthew Malcomson]

Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions.
This iclass encodes one of three variants by the most significant bit
set in a 3-bit value where only one bit may be set.

include/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
	iclass.

opcodes/ChangeLog:

2019-04-04  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_tsz_bhs iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_tsz_bhs iclass decode.
---
 include/opcode/aarch64.h |  1 +
 opcodes/aarch64-asm.c    |  6 ++++++
 opcodes/aarch64-dis.c    | 11 +++++++++++
 3 files changed, 18 insertions(+)

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 99da95c..2b78e97 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -597,6 +597,7 @@ enum aarch64_insn_class
   sve_size_013,
   sve_shift_tsz_hsd,
   sve_shift_tsz_bhsd,
+  sve_size_tsz_bhs,
   testbranch,
   cryptosm3,
   cryptosm4,
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index ad50598..afb0e5b 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1673,6 +1673,12 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
 		    aarch64_get_variant (inst) + 1, 0);
       break;
 
+    case sve_size_tsz_bhs:
+      insert_fields (&inst->value,
+		     (1 << aarch64_get_variant (inst)),
+		     0, 2, FLD_SVE_tszl_19, FLD_SVE_sz);
+      break;
+
     case sve_size_013:
       variant = aarch64_get_variant (inst);
       if (variant == 2)
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index b42e4d5..6b53a2c 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2843,6 +2843,17 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
 	}
       break;
 
+    case sve_size_tsz_bhs:
+      i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
+      while (i != 1)
+	{
+	  if (i & 1)
+	    return FALSE;
+	  i >>= 1;
+	  variant += 1;
+	}
+      break;
+
     case sve_shift_tsz_hsd:
       i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
       if (i == 0)
-- 
2.7.4