[committed][AArch64] Allow MOVPRFX to be used with FMOV

[Richard Sandiford]

The entry for the FMOV alias of FCPY was missing C_SCAN_MOVPRFX.
(The entry for FCPY itself was OK.)

This was the only /m-predicated instruction I could see that was
missing the flag.

Tested on aarch64-linux-gnu.  Applied to master and binutils-2_32-branch.

Richard


2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
	SVE FMOV alias of FCPY.

gas/
	* testsuite/gas/aarch64/sve-movprfx_27.s,
	* testsuite/gas/aarch64/sve-movprfx_27.d: New test.
------------------------------------------------------------------------------

Index: opcodes/aarch64-tbl.h
===================================================================
--- opcodes/aarch64-tbl.h	2019-07-02 10:55:23.996179534 +0100
+++ opcodes/aarch64-tbl.h	2019-07-02 10:55:27.656149579 +0100
@@ -3628,7 +3628,7 @@ struct aarch64_opcode aarch64_opcode_tab
   CORE_INSN ("ble", 0x5400000d, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO),
   /* SVE instructions.  */
   _SVE_INSN ("fmov", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_ALIAS, 0),
-  _SVE_INSN ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, 0),
+  _SVE_INSNC ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, C_SCAN_MOVPRFX, 0),
   _SVE_INSN ("mov", 0x04603000, 0xffe0fc00, sve_misc, OP_MOV_Z_Z, OP2 (SVE_Zd, SVE_Zn), OP_SVE_DD, F_ALIAS | F_MISC, 0),
   _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
   _SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0),
Index: gas/testsuite/gas/aarch64/sve-movprfx_27.s
===================================================================
--- /dev/null	2019-06-14 15:59:19.298479944 +0100
+++ gas/testsuite/gas/aarch64/sve-movprfx_27.s	2019-07-02 10:55:27.656149579 +0100
@@ -0,0 +1,11 @@
+	.text
+	.arch armv8-a+sve
+
+f:
+	movprfx z0, z1
+	fmov z0.s, p0/m, #1.0
+
+	movprfx z0, z1
+	fcpy z0.s, p0/m, #1.0
+
+	ret
Index: gas/testsuite/gas/aarch64/sve-movprfx_27.d
===================================================================
--- /dev/null	2019-06-14 15:59:19.298479944 +0100
+++ gas/testsuite/gas/aarch64/sve-movprfx_27.d	2019-07-02 10:55:27.656149579 +0100
@@ -0,0 +1,14 @@
+#source: sve-movprfx_27.s
+#as: -march=armv8-a+sve -I$srcdir/$subdir
+#objdump: -Dr -M notes
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+[^:]+:	0420bc20 	movprfx	z0, z1
+[^:]+:	0590ce00 	fmov	z0.s, p0/m, #1.0+(e\+00)?
+[^:]+:	0420bc20 	movprfx	z0, z1
+[^:]+:	0590ce00 	fmov	z0.s, p0/m, #1.0+(e\+00)?
+[^:]+:	d65f03c0 	ret