[PATCH v2 4/5] RISC-V: sb/uj format named b/j in latest spec
Kito Cheng
kito.cheng@sifive.com
Tue Jul 2 09:58:00 GMT 2019
- We also keep sb and uj for backward compatibility.
gas/ChangeLog:
* doc/c-riscv.texi (Instruction Formats): Add b and j type.
* testsuite/gas/riscv/insn.d: Add test case for b and j type.
* testsuite/gas/riscv/insn.s: Add Ditto.
opcode/ChangeLog:
* riscv-opc.c (riscv_insn_types): Add b and j type.
---
gas/doc/c-riscv.texi | 3 +++
gas/testsuite/gas/riscv/insn.d | 22 +++++++++++++++-------
gas/testsuite/gas/riscv/insn.s | 4 ++++
opcodes/riscv-opc.c | 8 ++++++++
4 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 5c30db1b83..a280ea216d 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -343,6 +343,8 @@ with the @samp{.insn} pseudo directive:
@item SB type: .insn sb opcode, func3, rd, rs1, symbol
@itemx SB type: .insn sb opcode, func3, rd, simm12(rs1)
+@itemx B type: .insn s opcode, func3, rd, rs1, symbol
+@itemx B type: .insn s opcode, func3, rd, simm12(rs1)
@verbatim
+------------+--------------+-----+-----+-------+-------------+-------------+--------+
| simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode |
@@ -359,6 +361,7 @@ with the @samp{.insn} pseudo directive:
@end verbatim
@item UJ type: .insn uj opcode, rd, symbol
+@itemx J type: .insn j opcode, rd, symbol
@verbatim
+------------+--------------+------------+---------------+----+-------------+
| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode |
diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
index 1e9ba3ac3c..0a2afa8dd8 100644
--- a/gas/testsuite/gas/riscv/insn.d
+++ b/gas/testsuite/gas/riscv/insn.d
@@ -13,34 +13,42 @@ Disassembly of section .text:
[^:]+:[ ]+00458503[ ]+lb[ ]+a0,4\(a1\)
[^:]+:[ ]+feb508e3[ ]+beq[ ]+a0,a1,0 \<target\>
[^:]+: R_RISCV_BRANCH[ ]+target
+[^:]+:[ ]+feb506e3[ ]+beq[ ]+a0,a1,0 \<target\>
+[^:]+: R_RISCV_BRANCH[ ]+target
[^:]+:[ ]+00a58223[ ]+sb[ ]+a0,4\(a1\)
[^:]+:[ ]+00fff537[ ]+lui[ ]+a0,0xfff
-[^:]+:[ ]+fe5ff56f[ ]+jal[ ]+a0,0 \<target\>
+[^:]+:[ ]+fe1ff56f[ ]+jal[ ]+a0,0 \<target\>
+[^:]+: R_RISCV_JAL[ ]+target
+[^:]+:[ ]+fddff56f[ ]+jal[ ]+a0,0 \<target\>
[^:]+: R_RISCV_JAL[ ]+target
[^:]+:[ ]+0511[ ]+addi[ ]+a0,a0,4
[^:]+:[ ]+852e[ ]+mv[ ]+a0,a1
[^:]+:[ ]+002c[ ]+addi[ ]+a1,sp,8
-[^:]+:[ ]+dde9[ ]+beqz[ ]+a1,0 \<target\>
+[^:]+:[ ]+d9e9[ ]+beqz[ ]+a1,0 \<target\>
[^:]+: R_RISCV_RVC_BRANCH[ ]+target
-[^:]+:[ ]+bfe1[ ]+j[ ]+0 \<target\>
+[^:]+:[ ]+bfc1[ ]+j[ ]+0 \<target\>
[^:]+: R_RISCV_RVC_JUMP[ ]+target
[^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
[^:]+:[ ]+00d58513[ ]+addi[ ]+a0,a1,13
[^:]+:[ ]+00a58567[ ]+jalr[ ]+a0,10\(a1\)
[^:]+:[ ]+00458503[ ]+lb[ ]+a0,4\(a1\)
-[^:]+:[ ]+fcb503e3[ ]+beq[ ]+a0,a1,0 \<target\>
+[^:]+:[ ]+fab50fe3[ ]+beq[ ]+a0,a1,0 \<target\>
+[^:]+: R_RISCV_BRANCH[ ]+target
+[^:]+:[ ]+fab50de3[ ]+beq[ ]+a0,a1,0 \<target\>
[^:]+: R_RISCV_BRANCH[ ]+target
[^:]+:[ ]+00a58223[ ]+sb[ ]+a0,4\(a1\)
[^:]+:[ ]+00fff537[ ]+lui[ ]+a0,0xfff
-[^:]+:[ ]+fbbff56f[ ]+jal[ ]+a0,0 \<target\>
+[^:]+:[ ]+fafff56f[ ]+jal[ ]+a0,0 \<target\>
+[^:]+: R_RISCV_JAL[ ]+target
+[^:]+:[ ]+fabff56f[ ]+jal[ ]+a0,0 \<target\>
[^:]+: R_RISCV_JAL[ ]+target
[^:]+:[ ]+0511[ ]+addi[ ]+a0,a0,4
[^:]+:[ ]+852e[ ]+mv[ ]+a0,a1
[^:]+:[ ]+002c[ ]+addi[ ]+a1,sp,8
[^:]+:[ ]+8d6d[ ]+and[ ]+a0,a0,a1
-[^:]+:[ ]+d5dd[ ]+beqz[ ]+a1,0 \<target\>
+[^:]+:[ ]+ddd9[ ]+beqz[ ]+a1,0 \<target\>
[^:]+: R_RISCV_RVC_BRANCH[ ]+target
-[^:]+:[ ]+b775[ ]+j[ ]+0 \<target\>
+[^:]+:[ ]+bf71[ ]+j[ ]+0 \<target\>
[^:]+: R_RISCV_RVC_JUMP[ ]+target
[^:]+:[ ]+68c58543[ ]+fmadd.s[ ]+fa0,fa1,fa2,fa3,rne
[^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
index 1b0915da4e..ce78bdf71c 100644
--- a/gas/testsuite/gas/riscv/insn.s
+++ b/gas/testsuite/gas/riscv/insn.s
@@ -4,9 +4,11 @@ target:
.insn i 0x67, 0, a0, 10(a1)
.insn i 0x3, 0, a0, 4(a1)
.insn sb 0x63, 0, a0, a1, target
+ .insn b 0x63, 0, a0, a1, target
.insn s 0x23, 0, a0, 4(a1)
.insn u 0x37, a0, 0xfff
.insn uj 0x6f, a0, target
+ .insn j 0x6f, a0, target
.insn ci 0x1, 0x0, a0, 4
.insn cr 0x2, 0x8, a0, a1
@@ -19,9 +21,11 @@ target:
.insn i JALR, 0, a0, 10(a1)
.insn i LOAD, 0, a0, 4(a1)
.insn sb BRANCH, 0, a0, a1, target
+ .insn b BRANCH, 0, a0, a1, target
.insn s STORE, 0, a0, 4(a1)
.insn u LUI, a0, 0xfff
.insn uj JAL, a0, target
+ .insn j JAL, a0, target
.insn ci C1, 0x0, a0, 4
.insn cr C2, 0x8, a0, a1
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 5b17279834..aa57cc950a 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -828,12 +828,20 @@ const struct riscv_opcode riscv_insn_types[] =
{"sb", 0, {"I", 0}, "O4,F3,s,T,p", 0, 0, match_opcode, 0 },
{"sb", 0, {"I", 0}, "O4,F3,S,T,p", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,s,t,p", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,S,t,p", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,s,T,p", 0, 0, match_opcode, 0 },
+{"b", 0, {"I", 0}, "O4,F3,S,T,p", 0, 0, match_opcode, 0 },
+
{"u", 0, {"I", 0}, "O4,d,u", 0, 0, match_opcode, 0 },
{"u", 0, {"I", 0}, "O4,D,u", 0, 0, match_opcode, 0 },
{"uj", 0, {"I", 0}, "O4,d,a", 0, 0, match_opcode, 0 },
{"uj", 0, {"I", 0}, "O4,D,a", 0, 0, match_opcode, 0 },
+{"j", 0, {"I", 0}, "O4,d,a", 0, 0, match_opcode, 0 },
+{"j", 0, {"I", 0}, "O4,D,a", 0, 0, match_opcode, 0 },
+
{"cr", 0, {"C", 0}, "O2,CF4,d,CV", 0, 0, match_opcode, 0 },
{"cr", 0, {"C", 0}, "O2,CF4,D,CV", 0, 0, match_opcode, 0 },
{"cr", 0, {"C", 0}, "O2,CF4,d,CT", 0, 0, match_opcode, 0 },
--
2.17.1
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