[PATCH 1/4] Arm64: correct 64-bit element fmmla encoding
Tamar Christina
Tamar.Christina@arm.com
Mon Dec 30 11:37:00 GMT 2019
Hi Jan,
I'm not a maintainer so you still need approval to commit but this change is correct.
Thanks for the fix!,
Tamar
> -----Original Message-----
> From: binutils-owner@sourceware.org <binutils-owner@sourceware.org>
> On Behalf Of Jan Beulich
> Sent: Friday, December 27, 2019 10:39
> To: binutils@sourceware.org
> Cc: Marcus Shawcroft <Marcus.Shawcroft@arm.com>; Mihail Ionescu
> <Mihail.Ionescu@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>
> Subject: [PATCH 1/4] Arm64: correct 64-bit element fmmla encoding
>
> There's just one bit of difference to the 32-bit element form, as per the
> documentation.
>
> gas/
> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>
> * testsuite/gas/aarch64/f64mm.d,
> testsuite/gas/aarch64/sve-movprfx-mm.d: Adjust expectations.
>
> opcodes/
> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>
> * opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
> FMMLA encoding.
> * opcodes/aarch64-dis-2.c: Re-generate.
>
> --- a/gas/testsuite/gas/aarch64/f64mm.d
> +++ b/gas/testsuite/gas/aarch64/f64mm.d
> @@ -6,8 +6,8 @@
> Disassembly of section \.text:
>
> 0+ <\.text>:
> - *[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d
> - *[0-9a-f]+: 64c0e400 fmmla z0\.d, z0\.d, z0\.d
> + *[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d
> + *[0-9a-f]+: 64e0e400 fmmla z0\.d, z0\.d, z0\.d
> *[0-9a-f]+: a43b17f1 ld1rob {z17\.b}, p5/z, \[sp, x27\]
> *[0-9a-f]+: a42003e0 ld1rob {z0\.b}, p0/z, \[sp, x0\]
> *[0-9a-f]+: a4bb17f1 ld1roh {z17\.h}, p5/z, \[sp, x27\]
> --- a/gas/testsuite/gas/aarch64/sve-movprfx-mm.d
> +++ b/gas/testsuite/gas/aarch64/sve-movprfx-mm.d
> @@ -21,4 +21,4 @@ Disassembly of section \.text:
> *[0-9a-f]+: 0420bc11 movprfx z17, z0
> *[0-9a-f]+: 64bbe6b1 fmmla z17\.s, z21\.s, z27\.s
> *[0-9a-f]+: 0420bc11 movprfx z17, z0
> - *[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d
> + *[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -5073,7 +5073,7 @@ struct aarch64_opcode aarch64_opcode_tab
> INT8MATMUL_SVE_INSNC ("usdot", 0x44a01800, 0xffe0fc00, sve_misc,
> OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0,
> C_SCAN_MOVPRFX, 0),
> INT8MATMUL_SVE_INSNC ("sudot", 0x44a01c00, 0xffe0fc00, sve_misc,
> OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0,
> C_SCAN_MOVPRFX, 0),
> F32MATMUL_SVE_INSNC ("fmmla", 0x64a0e400, 0xffe0fc00, sve_misc,
> OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX,
> 0),
> - F64MATMUL_SVE_INSNC ("fmmla", 0x64c0e400, 0xffe0fc00, sve_misc,
> OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX,
> 0),
> + F64MATMUL_SVE_INSNC ("fmmla", 0x64e0e400, 0xffe0fc00, sve_misc,
> OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX,
> 0),
> F64MATMUL_SVE_INSN ("ld1rob", 0xa4200000, 0xffe0e000, sve_misc, OP3
> (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0),
> F64MATMUL_SVE_INSN ("ld1roh", 0xa4a00000, 0xffe0e000, sve_misc, OP3
> (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HZU, F_OD(1), 0),
> F64MATMUL_SVE_INSN ("ld1row", 0xa5200000, 0xffe0e000, sve_misc, OP3
> (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SZU, F_OD(1), 0),
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