[PATCH, binutils, ARM, 15/16] Add support for VSCCLRM

[Andre Vieira (lists)]

Hi,

=== Context ===

This patch is part of a patch series to add support for Armv8.1-M
Mainline architecture. Its purpose is to add support for the new VSCCLRM
instruction.

=== Patch description ===

Like for CLRM, this patch aims to share as much logic with the similar
looking VLDM/VSTM. This is achieved by adding 2 new enumerator values in
enum reg_list_els for the single-precision and double-precision variants
of VSCCLRM and extending parse_vfp_reg_list () to deal with these types.
These behave like the existing REGLIST_VFP_S and REGLIST_VFP_D types
with extra logic to expect VPR as the last element in the register list.
The function is algo augmented with a new partial_match parameter to
indicate if any register other than VPR had already been parsed in the
register list so as to not try parsing the second variant if that's the
case and return the right error message.

The rest of the patch is the usual encoding function, new disassembler
table entries and format specifier and parsing, encoding and
disassembling tests.

It is worth mentioning that the new entry in the disassembler table was
added in the coprocessor-related table despite VSCCLRM always being
available even in FPU-less configurations. The main reason for this is
that VSCCLRM also match VLDMIA entry and must thus be tried first but
coprocessor entries are tried before T32 entries. It also makes sense
because it is in the same encoding space as coprocessor and VFP
instructions and is thus the natural place for someone to look for this
instruction.

Note: Both variants of VSCCLRM support D16-D31 registers but Armv8.1-M
Mainline overall does not. I have thus decided not to implement support
for these registers in order to keep the code simpler. It can always be
added later if needed.

ChangeLog entries are as follows:

*** gas/ChangeLog ***

2019-04-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment.
	(enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
	enumerators.
	(parse_vfp_reg_list): Add new partial_match parameter.  Set
	*partial_match to TRUE if at least one element in the register list has
	matched.  Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
	register lists which expect VPR as last element in the list.
	(s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new
	prototype.
	(s_arm_unwind_save_vfp): Likewise.
	(enum operand_parse_code): New OP_VRSDVLST enumerator.
	(parse_operands): Adapt call to parse_vfp_reg_list to new prototype.
	Handle new OP_VRSDVLST case.
	(do_t_vscclrm): New function.
	(insns): New entry for VSCCLRM instruction.
	* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM
	instructions.
	* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations
	for above instructions.
	* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM
	instruction.
	* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly
	for above instructions.

*** opcodes/ChangeLog ***

2019-04-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
	Add new entries for VSCCLRM instruction.
	(print_insn_coprocessor): Handle new %C format control code.
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