[PATCH. BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions.

[Sudakshina Das]

Hi

On 02/04/2019 17:06, Sudakshina Das wrote:
> Hi
> 
> This patch adds the new LDGM/STGM instructions of the
> Armv8.5-A Memory Tagging Extension. This is part of the changes
> that have been introduced recently in the 00bet10 release
> https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools 
> 
> 
> The instructions are as follows:
> LDGM Xt, [<Xn|SP>]
> https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldgm-load-tag-multiple 
> 
> 
> STGM Xt, [<Xn|SP>]
> https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/stgm-store-tag-multiple 
> 
> 
> For ease of review I have not added the regenerated files in the patch. 
> I will add those in my final commit.
> 
> Builds and reg tests all pass on aarch64-none-elf.
> 
> Is this ok for trunk? And for backport to 2.32?
> 
> Thanks
> Sudi
> 
> *** gas/ChangeLog ***
> 
> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>
> 
>      * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and 
> stgm.
>      * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
>      * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
>      * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
> 
> *** opcodes/ChangeLog ***
> 
> 2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>
> 
>      * aarch64-asm-2.c: Regenerated.
>      * aarch64-dis-2.c: Likewise.
>      * aarch64-opc-2.c: Likewise.
>      * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.

Hi

This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools

All of these instructions have an updated register operand (Xt -> <Xt|SP>)

- STG <Xt|SP>, [<Xn|SP>, #<simm>]
- STG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STG <Xt|SP>, [<Xn|SP>], #<simm>
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZG <Xt|SP>, [<Xn|SP>], #<simm>
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- ST2G <Xt|SP>, [<Xn|SP>], #<simm>
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZ2G <Xt|SP>, [<Xn|SP>], #<simm>

https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order

In order to accept <Rt|SP> a new operand type Rt_SP is introduced which 
has the same field as FLD_Rt but follows other semantics of Rn_SP.

For ease of review I have not added the regenerated files in the patch. 
I will add those in my final commit.

Builds and reg tests all pass on aarch64-none-elf.

Is this ok for trunk? And for backport to 2.32?

Thanks
Sudi

*** gas/ChangeLog ***

2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (process_omitted_operand): Add case for
	AARCH64_OPND_Rt_SP.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** include/ChangeLog ***

2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.

*** opcodes/ChangeLog ***

2019-xx-xx  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Add case for
	AARCH64_OPND_Rt_SP.
	(verify_constraints): Likewise.
	* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
	(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
	to accept Rt|SP as first operand.
	(AARCH64_OPERANDS): Add new Rt_SP.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: rb10869.patch
Type: text/x-patch
Size: 12306 bytes
Desc: rb10869.patch
URL: <https://sourceware.org/pipermail/binutils/attachments/20190402/51dbf2cd/attachment.bin>