[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers

[Jan Beulich]

>>> On 24.09.18 at 19:20, <sudi.das@arm.com> wrote:
> On 23/09/18 12:37, Jan Beulich wrote:
>>>>> Sudakshina Das <sudi.das@arm.com> 09/19/18 4:30 PM >>>
>>> --- a/opcodes/aarch64-opc.c
>>> +++ b/opcodes/aarch64-opc.c
>>> @@ -3714,6 +3714,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
>>> { "id_dfr0_el1",      CPENC(3,0,C0,C1,2),    F_REG_READ }, /* RO */
>>> { "id_pfr0_el1",      CPENC(3,0,C0,C1,0),    F_REG_READ }, /* RO */
>>> { "id_pfr1_el1",      CPENC(3,0,C0,C1,1),    F_REG_READ }, /* RO */
>>> +  { "id_pfr2_el1",      CPENC(3,0,C0,C3,4),    F_ARCHEXT },
>> 
>> Judging by the neighboring ones - isn't this new one supposed to have 
> F_REG_READ set?
> 
> Ah yes. Thanks for noticing. I will send out a modified patch soon.

Btw, I've also been wondering about the random number registers,
which look to support reads only as well.

Jan