[PATCH v2 0/7] x86: further template folding and misc improvements

[H.J. Lu]

On Thu, Sep 13, 2018 at 4:58 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Sep 13, 2018 at 1:59 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> On 12.09.18 at 23:19, <hjl.tools@gmail.com> wrote:
>>> On Wed, Sep 5, 2018 at 4:47 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> 1: add code comment on deprecated status of pseudo-suffixes
>>>> 2: improve operand reversal
>>>> 3: fold ILP32 output of "opts" tests
>>>> 4: extra operand reversal "opts" tests
>>>> 5: use D attribute also for SIMD templates
>>>> 6: also allow D on 3-operand insns
>>>> 7: drop unnecessary {,No}Rex64
>>>>
>>>> Besides the new last patch the main change here compared to v1 is
>>>> the splitting up of what is now patch 2. Patches 3 and 4 are therefore
>>>> optional now. Patches 5 and 6 have been approved already, but
>>>> can't go in without what is now patch 2.
>>>
>>> All looks good, except for
>>>
>>> https://sourceware.org/ml/binutils/2018-09/msg00026.html
>>>
>>> Please don't add new tests with the .s suffix.  Please use {load} or
>>> {store} instead.
>>
>> That's done in the earlier patch. I did submit the split parts in order
>> to have everything available, but I'll simply omit that patch when
>> committing (I take your response as "okay except for this one patch").
>
> That is OK.
>
> Thanks.
>
> --
> H.J.

But I see:

FAIL: i386 arch 10
FAIL: i386 arch 10 (lzcnt)
FAIL: i386 arch 10 (prefetchw)
FAIL: i386 arch 10 (bdver1)
FAIL: i386 arch 10 (bdver2)
FAIL: i386 arch 10 (bdver3)
FAIL: i386 arch 10 (bdver4)
FAIL: i386 arch 10 (btver1)
FAIL: i386 arch 10 (btver2)
FAIL: i386 noavx-1
FAIL: i386 noavx-3
FAIL: i386 AVX
FAIL: i386 AVX (Intel disassembly)
FAIL: x86-64 arch 2
FAIL: x86-64 arch 2 (lzcnt)
FAIL: x86-64 arch 2 (prefetchw)
FAIL: x86-64 arch 2 (bdver1)
FAIL: x86-64 arch 2 (bdver2)
FAIL: x86-64 arch 2 (bdver3)
FAIL: x86-64 arch 2 (bdver4)
FAIL: x86-64 arch 2 (btver1)
FAIL: x86-64 arch 2 (btver2)
FAIL: x86-64 AVX
FAIL: x86-64 AVX (Intel mode)
FAIL: x86-64 (ILP32) arch 2
FAIL: x86-64 (ILP32) AVX (Intel mode)
FAIL: x86-64 (ILP32) AVX


-- 
H.J.