[PATCH, BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A

[Sudakshina Das]

Hi Richard

On 30/10/18 09:26, Richard Earnshaw (lists) wrote:
> On 09/10/2018 18:23, Sudakshina Das wrote:
>> Hi
>>
>> This series adds support for ARMv8.5-A Memory Tagging Extensions.
>> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
>> Memory Tagging Extension (MTE) is an optional extension to
>> ARMv8.5-A and is enabled using the +memtag command line option.
>>
>> This patch adds the new command line option and the new feature macros.
>>
>> Testing done: Builds and reg tests all pass on aarch64-none-linux-gnu.
>>
>> Is this ok for trunk?
>>
>> Thanks
>> Sudi
>>
>>
>> *** include/ChangeLog ***
>>
>> 2018-xx-xx  Sudakshina Das  <sudi.das@arm.com>
>>
>> 	* opcode/aarch64.h (AARCH64_FEATURE_MTE): New.
>>
>> *** opcodes/ChangeLog ***
>>
>> 2018-xx-xx  Sudakshina Das  <sudi.das@arm.com>
>>
>> 	* aarch64-tbl.h (aarch64_feature_mte): New.
>> 	(MTE, MTE_INSN): New.
>>
>> *** gas/ChangeLog ***
>>
>> 2018-xx-xx  Sudakshina Das  <sudi.das@arm.com>
>>
>> 	* config/tc-aarch64.c (aarch64_features): Add "memtag"
>> 	as a new option.
>> 	* doc/c-aarch64.texi: Document the same.
>>
> 
> It's slightly confusing to be using memtag as the option name and
> mte/MTE internally.  Can we please use memtag/MEMTAG everywhere.
> 
> Otherwise, this is OK.
> 
> R.
> 
>>
>>
>> rb10003.patch
>>
>> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
>> index 4ae27f76ed9a9bdc6f058ca43f5f58b9cc30345f..08289be41696b5cb432dced0a562f87a09b0ee1e 100644
>> --- a/gas/config/tc-aarch64.c
>> +++ b/gas/config/tc-aarch64.c
>> @@ -8829,6 +8829,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
>>   			AARCH64_ARCH_NONE},
>>     {"ssbs",		AARCH64_FEATURE (AARCH64_FEATURE_SSBS, 0),
>>   			AARCH64_ARCH_NONE},
>> +  {"memtag",		AARCH64_FEATURE (AARCH64_FEATURE_MTE, 0),
>> +			AARCH64_ARCH_NONE},
>>     {NULL,		AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
>>   };
>>   
>> diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
>> index 4941c57c48113676cfbdd9ae38b691d468692179..f38fdf591a23c9c70f1b8e5fc5f183b5a21840e2 100644
>> --- a/gas/doc/c-aarch64.texi
>> +++ b/gas/doc/c-aarch64.texi
>> @@ -189,6 +189,8 @@ automatically cause those extensions to be disabled.
>>    @tab Enable ARMv8.5-A random number instructions.
>>   @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
>>    @tab Enable Speculative Store Bypassing Safe state read and write.
>> +@item @code{memtag} @tab ARMv8.5-A @tab No
>> + @tab Enable ARMv8.5-A Memory Tagging Extensions.
>>   @end multitable
>>   
>>   @node AArch64 Syntax
>> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
>> index 8487767349e3ec9d5d9d0ee8bc693c2dbe48f67c..47df4cbd5648aba180e28dbba5c2c72d80feb774 100644
>> --- a/include/opcode/aarch64.h
>> +++ b/include/opcode/aarch64.h
>> @@ -84,6 +84,8 @@ typedef uint32_t aarch64_insn;
>>   #define AARCH64_FEATURE_ID_PFR2		0x400000000000ULL
>>   /* SSBS mechanism enabled.  */
>>   #define AARCH64_FEATURE_SSBS		0x800000000000ULL
>> +/* Memory Tagging Extension.  */
>> +#define AARCH64_FEATURE_MTE		0x1000000000000ULL
>>   
>>   
>>   /* Architectures are the sum of the base and extensions.  */
>> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
>> index b73007d550118a7fe073674a456abba2fe09df85..59920856c4da7234c09f3572cc1adf629f32f67d 100644
>> --- a/opcodes/aarch64-tbl.h
>> +++ b/opcodes/aarch64-tbl.h
>> @@ -2171,6 +2171,8 @@ static const aarch64_feature_set aarch64_feature_predres =
>>     AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0);
>>   static const aarch64_feature_set aarch64_feature_bti =
>>     AARCH64_FEATURE (AARCH64_FEATURE_BTI, 0);
>> +static const aarch64_feature_set aarch64_feature_mte =
>> +  AARCH64_FEATURE (AARCH64_FEATURE_V8_5 | AARCH64_FEATURE_MTE, 0);
>>   
>>   
>>   #define CORE		&aarch64_feature_v8
>> @@ -2205,6 +2207,7 @@ static const aarch64_feature_set aarch64_feature_bti =
>>   #define SB		&aarch64_feature_sb
>>   #define PREDRES		&aarch64_feature_predres
>>   #define BTI		&aarch64_feature_bti
>> +#define MTE		&aarch64_feature_mte
>>   
>>   #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
>>     { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
>> @@ -2268,6 +2271,8 @@ static const aarch64_feature_set aarch64_feature_bti =
>>     { NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL }
>>   #define BTI_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
>>     { NAME, OPCODE, MASK, CLASS, 0, BTI, OPS, QUALS, FLAGS, 0, 0, NULL }
>> +#define MTE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
>> +  { NAME, OPCODE, MASK, CLASS, 0, MTE, OPS, QUALS, FLAGS, 0, 0, NULL }
>>   
>>   struct aarch64_opcode aarch64_opcode_table[] =
>>   {
>>
>>
> 

Thank you for the reviews. The entire series in now committed.

Thanks
Sudi