[PATCH, BINUTILS, AARCH64, 6/8] Add Bulk Allocation Tag instructions in Memory Tagging Extension

[Sudakshina Das]

On 02/11/18 16:10, Sudakshina Das wrote:
> Hi Richard
> 
> On 30/10/18 10:23, Richard Earnshaw (lists) wrote:
>> On 09/10/2018 18:25, Sudakshina Das wrote:
>>> Hi
>>>
>>> This patch is part of the patch series to add support for ARMv8.5-A
>>> Memory Tagging Extensions.
>>> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) 
>>>
>>>
>>> Memory Tagging Extension (MTE) is an optional extension to
>>> ARMv8.5-A and is enabled using the +memtag command line option.
>>>
>>> This patch add support to the Bulk Allocation Tag instructions from
>>> MTE. These are the following instructions added in this patch:
>>> - LDGV <Xt>, [<Xn|SP>]!
>>> - STGV <Xt>, [<Xn|SP>]!
>>>
>>> This needed a new kind of operand for the new addressing [<Xn|SP>]!
>>> since this has no offset and only takes a pre-indexed version.
>>> Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced.
>>> (AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does
>>> not allow writeback). We also needed new encoding and decoding
>>> functions to be able to do the same.
>>>
>>> where
>>> <Xt> : Is the 64-bit destination GPR.
>>> <Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
>>>
>>> Testing done: Builds and reg tests all pass on aarch64-none-linux-gnu.
>>> Added test.
>>>
>>> Is this ok for trunk?
>>>
>>> Thanks
>>> Sudi
>>>
>>> *** include/ChangeLog ***
>>>
>>> 2018-xx-xx  Sudakshina Das  <sudi.das@arm.com>
>>>
>>>      * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
>>>      (aarch64_insn_class): Add ldstgv_indexed.
>>>
>>> *** opcodes/ChangeLog ***
>>>
>>> 2018-xx-xx  Sudakshina Das  <sudi.das@arm.com>
>>>
>>>      * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
>>>      * aarch64-asm.h (ins_addr_simple_2): Declare the above.
>>>      * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
>>>      * aarch64-dis.h (ext_addr_simple_2): Declare the above.
>>>      * aarch64-opc.c (operand_general_constraint_met_p): Add case for
>>>      AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
>>>      (aarch64_print_operand): Add case for
>>>      AARCH64_OPND_ADDR_SIMPLE_2.
>>>      * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
>>>      (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
>>>      * aarch64-asm-2.c: Regenarated.
>>>      * aarch64-dis-2.c: Regenerated.
>>>      * aarch64-opc-2.c: Regenerated.
>>>
>>> *** gas/ChangeLog ***
>>>
>>> 2018-xx-xx  Sudakshina Das  <sudi.das@arm.com>
>>>
>>>      * config/tc-aarch64.c (parse_operands): Add switch case for
>>>      AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it.
>>>      * testsuite/gas/aarch64/armv8_5-a-mte.s: Add tests for ldgv and
>>>      stgv.
>>>      * testsuite/gas/aarch64/armv8_5-a-mte.d: Likewise.
>>>
>>>
>>
>> Same issue re mte.
>>
>> I'd also like to see some error tests, eg for missing the mandatory
>> write-back character.
>>
>> R.
>>
> 
> *** include/ChangeLog ***
> 
> 2018-xx-xx  Sudakshina Das  <sudi.das@arm.com>
> 
>      * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
>      (aarch64_insn_class): Add ldstgv_indexed.
> 
> *** opcodes/ChangeLog ***
> 
> 2018-xx-xx  Sudakshina Das  <sudi.das@arm.com>
> 
>      * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
>      * aarch64-asm.h (ins_addr_simple_2): Declare the above.
>      * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
>      * aarch64-dis.h (ext_addr_simple_2): Declare the above.
>      * aarch64-opc.c (operand_general_constraint_met_p): Add case for
>      AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
>      (aarch64_print_operand): Add case for
>      AARCH64_OPND_ADDR_SIMPLE_2.
>      * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
>      (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
>      * aarch64-asm-2.c: Regenerated.
>      * aarch64-dis-2.c: Regenerated.
>      * aarch64-opc-2.c: Regenerated.
> 
> *** gas/ChangeLog ***
> 
> 2018-xx-xx  Sudakshina Das  <sudi.das@arm.com>
> 
>      * config/tc-aarch64.c (parse_operands): Add switch case for
>      AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it.
>      (warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv.
>      * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv
>      and stgv.
>      * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
>      * testsuite/gas/aarch64/illegal-memtag.s: Likewise
>      * testsuite/gas/aarch64/illegal-memtag.l: Likewise
> 
New patch. Changelog still applies.

Sudi

> Thanks
> Sudi
> 


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