[PATCH, BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Extension
Sudakshina Das
Sudi.Das@arm.com
Thu Nov 8 10:34:00 GMT 2018
Hi Richard
On 06/11/18 15:29, Richard Earnshaw (lists) wrote:
> On 02/11/2018 16:08, Sudakshina Das wrote:
>> Hi Richard
>>
>> On 30/10/18 09:39, Richard Earnshaw (lists) wrote:
>>> On 09/10/2018 18:23, Sudakshina Das wrote:
>>>> Hi
>>>>
>>>> This patch is part of the patch series to add support for ARMv8.5-A
>>>> Memory Tagging Extensions.
>>>> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
>>>> Memory Tagging Extension (MTE) is an optional extension to
>>>> ARMv8.5-A and is enabled using the +memtag command line option.
>>>>
>>>> This patch add support to the Tag generation instructions from
>>>> MTE. These are the following instructions added in this patch:
>>>> - IRG <Xd|SP>, <Xn|SP>{, Xm}
>>>> - ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
>>>> - SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
>>>> - GMI <Xd>, <Xn|SP>, <Xm>
>>>>
>>>> where
>>>> <Xd|SP> : Is the 64-bit destination GPR or Stack pointer.
>>>> <Xn|SP> : Is the 64-bit source GPR or Stack pointer.
>>>> <uimm1> : Is the unsigned immediate, a multiple of 16
>>>> in the range 0 to 1008.
>>>> <uimm2> : Is the unsigned immediate, in the range 0 to 15.
>>>>
>>>> Testing done: Builds and reg tests all pass on aarch64-none-linux-gnu.
>>>> Added test.
>>>>
>>>> Is this ok for trunk>>>
>>>> Thanks
>>>> Sudi
>>>>
>>>> *** include/ChangeLog ***
>>>>
>>>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>>>
>>>> * opcode/aarch64.h (aarch64_opnd): Add
>>>> AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
>>>>
>>>> *** opcodes/ChangeLog ***
>>>>
>>>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>>>
>>>> * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
>>>> (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
>>>> * aarch64-opc.c (fields): Add entry for imm4_3.
>>>> (operand_general_constraint_met_p): Add cases for
>>>> AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
>>>> (aarch64_print_operand): Likewise.
>>>> * aarch64-tbl.h (QL_ADDG): New.
>>>> (aarch64_opcode_table): Add addg, subg, irg and gmi.
>>>> (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
>>>> * aarch64-asm.c (aarch64_ins_imm): Add case for
>>>> operand_need_shift_by_four.
>>>> * aarch64-asm-2.c: Regenarated.
>>>> * aarch64-dis-2.c: Regenerated.
>>>> * aarch64-opc-2.c: Regenerated.
>>>>
>>>> *** gas/ChangeLog ***
>>>>
>>>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>>>
>>>> * config/tc-aarch64.c (parse_operands): Add switch case for
>>>> AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
>>>> * testsuite/gas/aarch64/armv8_5-a-mte.s: New.
>>>> * testsuite/gas/aarch64/armv8_5-a-mte.d: Likewise.
>>>>
>>>>
>>>>
>>>
>>> Urgh! We really need to get rid of those ridiculous autogenerated files
>>> from the source tree...
>>>
>>
>> Agreed, I will try to move these after I commit these.
>>
>>> Same issue as patch 1 re mte/memtag.
>>
>> Done
>>
>>>
>>> aarch64-opc.c:
>>> + case AARCH64_OPND_UIMM10:
>>> + /* Scaled unsigned 10 bits immediate offset. */
>>> + if (!value_in_range_p (opnd->imm.value, 0, 1008))
>>> + {
>>> + set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
>>> + return 0;
>>> + }
>>> + if (!value_aligned_p (opnd->imm.value, 16))
>>> + {
>>> +
>>>
>>> Blank line between independent if clauses.
>>
>> Done.
>>
>> Thanks you for test case suggestions. I have also updated the tests and
>> added a test for the illegal tests. The illegal testing has also
>> allowed me to fish out a couple of bugs.
>>
>> I have changed the general format of the positive tests to make it
>> better to read. All macros are moved on top and every instruction has
>> the following testing pattern:
>> 1) Base test with x0 and #0 depending on the instruction
>> 2) Macro call to add some random tests of different combinations.
>> 3) Special casing some SP register and immediate corner cases depending
>> on the instruction.
>>
>> All of these tests are cross referenced with a different disassembler to
>> make sure of the encodings. This applies to the tests of all the patches
>> that I am updating.
>>
>
> Thanks for the updates. I don't see, however, any tests for when SP is
> valid as an operand, or any tests for when Xzr should be accepted/rejected.
>
I have added xzr both for positive and negative tests
SP was already there, but I have further reduces the positive test cases
to not include too much macros and only test one field at a time as you
suggested offline.
I am attaching the new patches without the regenerated files and there
is no change to the changelog.
Thanks
Sudi
PS: This applies to all the tests in the patch series 2/8 - 6/8
> R.
>
>> *** include/ChangeLog ***
>>
>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>
>> * opcode/aarch64.h (aarch64_opnd): Add
>> AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
>>
>> *** opcodes/ChangeLog ***
>>
>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>
>> * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
>> (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
>> * aarch64-opc.c (fields): Add entry for imm4_3.
>> (operand_general_constraint_met_p): Add cases for
>> AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
>> (aarch64_print_operand): Likewise.
>> * aarch64-tbl.h (QL_ADDG): New.
>> (aarch64_opcode_table): Add addg, subg, irg and gmi.
>> (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
>> * aarch64-asm.c (aarch64_ins_imm): Add case for
>> operand_need_shift_by_four.
>> * aarch64-asm-2.c: Regenerated.
>> * aarch64-dis-2.c: Regenerated.
>> * aarch64-opc-2.c: Regenerated.
>>
>> *** gas/ChangeLog ***
>>
>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>
>> * config/tc-aarch64.c (parse_operands): Add switch case for
>> AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
>> * testsuite/gas/aarch64/armv8_5-a-memtag.s: New.
>> * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
>> * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
>> * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
>> * testsuite/gas/aarch64/illegal-memtag.d: Likewise.
>>
>> Thanks
>> Sudi
>>
>>>
>>> Otherwise OK.
>>>
>>> R.
>>>
>>
>>
>>
>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: rb10006.patch
Type: text/x-patch
Size: 13711 bytes
Desc: rb10006.patch
URL: <https://sourceware.org/pipermail/binutils/attachments/20181108/11840da7/attachment.bin>
More information about the Binutils
mailing list