[PATCH] x86: don't emit REX.W for SLDT and STR

[Jan Beulich]

Just like for other selector register reads, they're unnecessary and
should hence be avoided.

gas/
2018-05-30  Jan Beulich  <jbeulich@suse.com>

	* testsuite/gas/i386/ilp32/x86-64-opcode.d,
	testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.

opcodes/
2018-05-30  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (sldt, str): Add NoRex64.
	* i386-tbl.h: Re-generate.

--- a/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d
@@ -269,7 +269,7 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	41 0f 01 38          	invlpg \(%r8\)
 [ 	]*[a-f0-9]+:	0f 01 38             	invlpg \(%rax\)
 [ 	]*[a-f0-9]+:	0f 00 c0             	sldt   %eax
-[ 	]*[a-f0-9]+:	48 0f 00 c0          	sldt   %rax
+[ 	]*[a-f0-9]+:	0f 00 c0             	sldt   %eax
 [ 	]*[a-f0-9]+:	66 0f 00 c0          	sldt   %ax
 [ 	]*[a-f0-9]+:	0f 00 00             	sldt   \(%rax\)
 [ 	]*[a-f0-9]+:	e6 00                	out    %al,\$0x0
@@ -294,7 +294,7 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 e0             	smsw   %eax
 [ 	]*[a-f0-9]+:	66 0f 01 e0          	smsw   %ax
 [ 	]*[a-f0-9]+:	0f 01 20             	smsw   \(%rax\)
-[ 	]*[a-f0-9]+:	48 0f 00 c8          	str    %rax
+[ 	]*[a-f0-9]+:	0f 00 c8             	str    %eax
 [ 	]*[a-f0-9]+:	0f 00 c8             	str    %eax
 [ 	]*[a-f0-9]+:	66 0f 00 c8          	str    %ax
 [ 	]*[a-f0-9]+:	0f 00 08             	str    \(%rax\)
--- a/gas/testsuite/gas/i386/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -268,7 +268,7 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	41 0f 01 38          	invlpg \(%r8\)
 [ 	]*[a-f0-9]+:	0f 01 38             	invlpg \(%rax\)
 [ 	]*[a-f0-9]+:	0f 00 c0             	sldt   %eax
-[ 	]*[a-f0-9]+:	48 0f 00 c0          	sldt   %rax
+[ 	]*[a-f0-9]+:	0f 00 c0             	sldt   %eax
 [ 	]*[a-f0-9]+:	66 0f 00 c0          	sldt   %ax
 [ 	]*[a-f0-9]+:	0f 00 00             	sldt   \(%rax\)
 [ 	]*[a-f0-9]+:	e6 00                	out    %al,\$0x0
@@ -293,7 +293,7 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 e0             	smsw   %eax
 [ 	]*[a-f0-9]+:	66 0f 01 e0          	smsw   %ax
 [ 	]*[a-f0-9]+:	0f 01 20             	smsw   \(%rax\)
-[ 	]*[a-f0-9]+:	48 0f 00 c8          	str    %rax
+[ 	]*[a-f0-9]+:	0f 00 c8             	str    %eax
 [ 	]*[a-f0-9]+:	0f 00 c8             	str    %eax
 [ 	]*[a-f0-9]+:	66 0f 00 c8          	str    %ax
 [ 	]*[a-f0-9]+:	0f 00 08             	str    \(%rax\)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -516,11 +516,11 @@ sgdt, 1, 0xf01, 0x0, 2, Cpu286|CpuNo64,
 sgdt, 1, 0xf01, 0x0, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
 sidt, 1, 0xf01, 0x1, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
 sidt, 1, 0xf01, 0x1, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-sldt, 1, 0xf00, 0x0, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
+sldt, 1, 0xf00, 0x0, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64 }
 sldt, 1, 0xf00, 0x0, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex }
 smsw, 1, 0xf01, 0x4, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
 smsw, 1, 0xf01, 0x4, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex }
-str, 1, 0xf00, 0x1, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
+str, 1, 0xf00, 0x1, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64 }
 str, 1, 0xf00, 0x1, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex }
 
 verr, 1, 0xf00, 0x4, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex }