[PATCH, committed] x86: Replace AddrPrefixOp0 with AddrPrefixOpReg

[Jan Beulich]

>>> "H.J. Lu" <hjl.tools@gmail.com> 05/09/18 2:45 PM >>>
>On Wed, May 9, 2018 at 5:34 AM, Jan Beulich <jbeulich@suse.com> wrote:
>>>>> "H.J. Lu" <hjl.tools@gmail.com> 05/09/18 1:58 PM >>>
>>>On Tue, May 8, 2018 at 11:28 PM, Jan Beulich <jbeulich@suse.com> wrote:
>>>>>>> "H.J. Lu" <hongjiu.lu@intel.com> 05/07/18 7:01 PM >>>
>>>>>--- a/gas/config/tc-i386.c
>>>>>+++ b/gas/config/tc-i386.c
>>>>>@@ -5997,14 +5997,18 @@ process_suffix (void)
>>>>>/* Now select between word & dword operations via the operand
>>>>>size prefix, except for instructions that will ignore this
>>>>>prefix anyway.  */
>>>>>-      if (i.tm.opcode_modifier.addrprefixop0)
>>>>>+      if (i.reg_operands > 0
>>>>>+        && i.types[0].bitfield.reg
>>>>>+        && i.tm.opcode_modifier.addrprefixopreg
>>>>>+        && (i.tm.opcode_modifier.immext
>>>>>+            || i.operands == 1))
>>>>
>>>> What is this comparison against 1 for? All the single operand SVM insns
>>>> have ImmExt set.
>>>
>>>It is for cpumovdir64b which has 2 operands and doesn't use 0x66 prefix.
>>
>> That makes it even less clear to me - why " || i.operands == 1" when we talk
>> about a 2-operand insn here?
>
>Some instructions with 1 register operand addrprefixopreg doesn't have
>opcode_modifier.immext.  But they need 0x66 prefix.

Would you mind pointing out at least one example? It looks to me as if they
all have ImmExt set.

Jan