[PATCH 2/5] x86: improve SIMD to‑scalar‑int conversion insn handling

Jan Beulich JBeulich@suse.com
Wed Mar 21 14:20:00 GMT 2018


In the course of folding their patterns (possible now that the pointless
and partly even bogus VecESize are no longer in the way) I've noticed
that vcvt*2usi, other than their vcvt*2si counterparts, didn't allow for
any suffixes. As with all insns touching GPRs, these should be permitted
even if they're not required for determining operand sizes. In turn I've
noticed that only a very limited set of cases had a suffix added in
disassembly with -Msuffix, while all suffixes should be output in that
mode.

gas/
2018-03-21  Jan Beulich  <jbeulich@suse.com>

	* testsuite/gas/i386/cvt-2si.d, testsuite/gas/i386/cvt-2si.s:
	New.
	* testsuite/gas/i386/i386.exp: Run new test.
	* testsuite/gas/i386/ilp32/x86-64-simd-suffix.d,
	testsuite/gas/i386/simd-suffix.d,
	testsuite/gas/i386/x86-64-simd-suffix.d: Adjust expectations.

opcodes/
2018-03-21  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (prefix_table): Replace Y by S for cvt*2si.
	(vex_len_table): Replace Y by S for vcvt*2si.
	(putop): Replace plain 'Y' handling by abort().
	* i386-dis-evex.h (evex_table): Replace Y by S for vcvt*2si.
	* i386-opc.tbl (vcvt*d2si): Fold AVX512 forms. Add ToDword.
	(vcvt*s2si): Fold AVX512 forms. Add ToQword.
	* i386-tlb.h: Re-generate.

--- /dev/null
+++ b/gas/testsuite/gas/i386/cvt-2si.d
@@ -0,0 +1,80 @@
+#objdump: -dwMsuffix
+#name: x86 convert SIMD to scalar int
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <cvt>:
+[ 	]*[0-9a-f]+:	f2 0f 2d 00[ 	]+cvtsd2sil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	f2 0f 2d c0[ 	]+cvtsd2sil %xmm0,%eax
+[ 	]*[0-9a-f]+:	f2 48 0f 2d 00[ 	]+cvtsd2siq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	f2 48 0f 2d c0[ 	]+cvtsd2siq %xmm0,%rax
+[ 	]*[0-9a-f]+:	f3 0f 2d 00[ 	]+cvtss2sil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	f3 0f 2d c0[ 	]+cvtss2sil %xmm0,%eax
+[ 	]*[0-9a-f]+:	f3 48 0f 2d 00[ 	]+cvtss2siq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	f3 48 0f 2d c0[ 	]+cvtss2siq %xmm0,%rax
+[ 	]*[0-9a-f]+:	f2 0f 2c 00[ 	]+cvttsd2sil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	f2 0f 2c c0[ 	]+cvttsd2sil %xmm0,%eax
+[ 	]*[0-9a-f]+:	f2 48 0f 2c 00[ 	]+cvttsd2siq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	f2 48 0f 2c c0[ 	]+cvttsd2siq %xmm0,%rax
+[ 	]*[0-9a-f]+:	f3 0f 2c 00[ 	]+cvttss2sil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	f3 0f 2c c0[ 	]+cvttss2sil %xmm0,%eax
+[ 	]*[0-9a-f]+:	f3 48 0f 2c 00[ 	]+cvttss2siq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	f3 48 0f 2c c0[ 	]+cvttss2siq %xmm0,%rax
+[ 	]*[0-9a-f]+:	c5 fb 2d 00[ 	]+vcvtsd2sil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	62 f1 7f 08 2d 00[ 	]+vcvtsd2sil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	62 b1 7f 08 2d c0[ 	]+vcvtsd2sil %xmm16,%eax
+[ 	]*[0-9a-f]+:	62 f1 7f 18 2d c0[ 	]+vcvtsd2sil \{rn-sae\},%xmm0,%eax
+[ 	]*[0-9a-f]+:	c4 e1 fb 2d 00[ 	]+vcvtsd2siq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	62 f1 ff 08 2d 00[ 	]+vcvtsd2siq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	62 b1 ff 08 2d c0[ 	]+vcvtsd2siq %xmm16,%rax
+[ 	]*[0-9a-f]+:	62 f1 ff 18 2d c0[ 	]+vcvtsd2siq \{rn-sae\},%xmm0,%rax
+[ 	]*[0-9a-f]+:	c5 fa 2d 00[ 	]+vcvtss2sil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	62 f1 7e 08 2d 00[ 	]+vcvtss2sil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	62 b1 7e 08 2d c0[ 	]+vcvtss2sil %xmm16,%eax
+[ 	]*[0-9a-f]+:	62 f1 7e 18 2d c0[ 	]+vcvtss2sil \{rn-sae\},%xmm0,%eax
+[ 	]*[0-9a-f]+:	c4 e1 fa 2d 00[ 	]+vcvtss2siq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	62 f1 fe 08 2d 00[ 	]+vcvtss2siq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	62 b1 fe 08 2d c0[ 	]+vcvtss2siq %xmm16,%rax
+[ 	]*[0-9a-f]+:	62 f1 fe 18 2d c0[ 	]+vcvtss2siq \{rn-sae\},%xmm0,%rax
+[ 	]*[0-9a-f]+:	62 f1 7f 08 79 00[ 	]+vcvtsd2usil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	62 b1 7f 08 79 c0[ 	]+vcvtsd2usil %xmm16,%eax
+[ 	]*[0-9a-f]+:	62 f1 7f 18 79 c0[ 	]+vcvtsd2usil \{rn-sae\},%xmm0,%eax
+[ 	]*[0-9a-f]+:	62 f1 ff 08 79 00[ 	]+vcvtsd2usiq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	62 b1 ff 08 79 c0[ 	]+vcvtsd2usiq %xmm16,%rax
+[ 	]*[0-9a-f]+:	62 f1 ff 18 79 c0[ 	]+vcvtsd2usiq \{rn-sae\},%xmm0,%rax
+[ 	]*[0-9a-f]+:	62 f1 7e 08 79 00[ 	]+vcvtss2usil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	62 b1 7e 08 79 c0[ 	]+vcvtss2usil %xmm16,%eax
+[ 	]*[0-9a-f]+:	62 f1 7e 18 79 c0[ 	]+vcvtss2usil \{rn-sae\},%xmm0,%eax
+[ 	]*[0-9a-f]+:	62 f1 fe 08 79 00[ 	]+vcvtss2usiq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	62 b1 fe 08 79 c0[ 	]+vcvtss2usiq %xmm16,%rax
+[ 	]*[0-9a-f]+:	62 f1 fe 18 79 c0[ 	]+vcvtss2usiq \{rn-sae\},%xmm0,%rax
+[ 	]*[0-9a-f]+:	c5 fb 2c 00[ 	]+vcvttsd2sil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	62 f1 7f 08 2c 00[ 	]+vcvttsd2sil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	62 b1 7f 08 2c c0[ 	]+vcvttsd2sil %xmm16,%eax
+[ 	]*[0-9a-f]+:	62 f1 7f 18 2c c0[ 	]+vcvttsd2sil \{sae\},%xmm0,%eax
+[ 	]*[0-9a-f]+:	c4 e1 fb 2c 00[ 	]+vcvttsd2siq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	62 f1 ff 08 2c 00[ 	]+vcvttsd2siq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	62 b1 ff 08 2c c0[ 	]+vcvttsd2siq %xmm16,%rax
+[ 	]*[0-9a-f]+:	62 f1 ff 18 2c c0[ 	]+vcvttsd2siq \{sae\},%xmm0,%rax
+[ 	]*[0-9a-f]+:	c5 fa 2c 00[ 	]+vcvttss2sil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	62 f1 7e 08 2c 00[ 	]+vcvttss2sil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	62 b1 7e 08 2c c0[ 	]+vcvttss2sil %xmm16,%eax
+[ 	]*[0-9a-f]+:	62 f1 7e 18 2c c0[ 	]+vcvttss2sil \{sae\},%xmm0,%eax
+[ 	]*[0-9a-f]+:	c4 e1 fa 2c 00[ 	]+vcvttss2siq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	62 f1 fe 08 2c 00[ 	]+vcvttss2siq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	62 b1 fe 08 2c c0[ 	]+vcvttss2siq %xmm16,%rax
+[ 	]*[0-9a-f]+:	62 f1 fe 18 2c c0[ 	]+vcvttss2siq \{sae\},%xmm0,%rax
+[ 	]*[0-9a-f]+:	62 f1 7f 08 78 00[ 	]+vcvttsd2usil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	62 b1 7f 08 78 c0[ 	]+vcvttsd2usil %xmm16,%eax
+[ 	]*[0-9a-f]+:	62 f1 7f 18 78 c0[ 	]+vcvttsd2usil \{sae\},%xmm0,%eax
+[ 	]*[0-9a-f]+:	62 f1 ff 08 78 00[ 	]+vcvttsd2usiq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	62 b1 ff 08 78 c0[ 	]+vcvttsd2usiq %xmm16,%rax
+[ 	]*[0-9a-f]+:	62 f1 ff 18 78 c0[ 	]+vcvttsd2usiq \{sae\},%xmm0,%rax
+[ 	]*[0-9a-f]+:	62 f1 7e 08 78 00[ 	]+vcvttss2usil \(%rax\),%eax
+[ 	]*[0-9a-f]+:	62 b1 7e 08 78 c0[ 	]+vcvttss2usil %xmm16,%eax
+[ 	]*[0-9a-f]+:	62 f1 7e 18 78 c0[ 	]+vcvttss2usil \{sae\},%xmm0,%eax
+[ 	]*[0-9a-f]+:	62 f1 fe 08 78 00[ 	]+vcvttss2usiq \(%rax\),%rax
+[ 	]*[0-9a-f]+:	62 b1 fe 08 78 c0[ 	]+vcvttss2usiq %xmm16,%rax
+[ 	]*[0-9a-f]+:	62 f1 fe 18 78 c0[ 	]+vcvttss2usiq \{sae\},%xmm0,%rax
--- /dev/null
+++ b/gas/testsuite/gas/i386/cvt-2si.s
@@ -0,0 +1,87 @@
+# vcvts{d,s}2usi{l,q} fail to assemble
+# almost all suffixes missing for -Msuffix disassembly
+	.text
+cvt:
+	cvtsd2sil	(%rax), %eax
+	cvtsd2sil	%xmm0, %eax
+	cvtsd2siq	(%rax), %rax
+	cvtsd2siq	%xmm0, %rax
+
+	cvtss2sil	(%rax), %eax
+	cvtss2sil	%xmm0, %eax
+	cvtss2siq	(%rax), %rax
+	cvtss2siq	%xmm0, %rax
+
+	cvttsd2sil	(%rax), %eax
+	cvttsd2sil	%xmm0, %eax
+	cvttsd2siq	(%rax), %rax
+	cvttsd2siq	%xmm0, %rax
+
+	cvttss2sil	(%rax), %eax
+	cvttss2sil	%xmm0, %eax
+	cvttss2siq	(%rax), %rax
+	cvttss2siq	%xmm0, %rax
+
+	vcvtsd2sil	(%rax), %eax
+{evex}	vcvtsd2sil	(%rax), %eax
+	vcvtsd2sil	%xmm16, %eax
+	vcvtsd2sil	{rn-sae}, %xmm0, %eax
+	vcvtsd2siq	(%rax), %rax
+{evex}	vcvtsd2siq	(%rax), %rax
+	vcvtsd2siq	%xmm16, %rax
+	vcvtsd2siq	{rn-sae}, %xmm0, %rax
+
+	vcvtss2sil	(%rax), %eax
+{evex}	vcvtss2sil	(%rax), %eax
+	vcvtss2sil	%xmm16, %eax
+	vcvtss2sil	{rn-sae}, %xmm0, %eax
+	vcvtss2siq	(%rax), %rax
+{evex}	vcvtss2siq	(%rax), %rax
+	vcvtss2siq	%xmm16, %rax
+	vcvtss2siq	{rn-sae}, %xmm0, %rax
+
+	vcvtsd2usil	(%rax), %eax
+	vcvtsd2usil	%xmm16, %eax
+	vcvtsd2usil	{rn-sae}, %xmm0, %eax
+	vcvtsd2usiq	(%rax), %rax
+	vcvtsd2usiq	%xmm16, %rax
+	vcvtsd2usiq	{rn-sae}, %xmm0, %rax
+
+	vcvtss2usil	(%rax), %eax
+	vcvtss2usil	%xmm16, %eax
+	vcvtss2usil	{rn-sae}, %xmm0, %eax
+	vcvtss2usiq	(%rax), %rax
+	vcvtss2usiq	%xmm16, %rax
+	vcvtss2usiq	{rn-sae}, %xmm0, %rax
+
+	vcvttsd2sil	(%rax), %eax
+{evex}	vcvttsd2sil	(%rax), %eax
+	vcvttsd2sil	%xmm16, %eax
+	vcvttsd2sil	{sae}, %xmm0, %eax
+	vcvttsd2siq	(%rax), %rax
+{evex}	vcvttsd2siq	(%rax), %rax
+	vcvttsd2siq	%xmm16, %rax
+	vcvttsd2siq	{sae}, %xmm0, %rax
+
+	vcvttss2sil	(%rax), %eax
+{evex}	vcvttss2sil	(%rax), %eax
+	vcvttss2sil	%xmm16, %eax
+	vcvttss2sil	{sae}, %xmm0, %eax
+	vcvttss2siq	(%rax), %rax
+{evex}	vcvttss2siq	(%rax), %rax
+	vcvttss2siq	%xmm16, %rax
+	vcvttss2siq	{sae}, %xmm0, %rax
+
+	vcvttsd2usil	(%rax), %eax
+	vcvttsd2usil	%xmm16, %eax
+	vcvttsd2usil	{sae}, %xmm0, %eax
+	vcvttsd2usiq	(%rax), %rax
+	vcvttsd2usiq	%xmm16, %rax
+	vcvttsd2usiq	{sae}, %xmm0, %rax
+
+	vcvttss2usil	(%rax), %eax
+	vcvttss2usil	%xmm16, %eax
+	vcvttss2usil	{sae}, %xmm0, %eax
+	vcvttss2usiq	(%rax), %rax
+	vcvttss2usiq	%xmm16, %rax
+	vcvttss2usiq	{sae}, %xmm0, %rax
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -701,6 +701,7 @@ if [expr ([istarget "i*86-*-*"] || [ista
     run_dump_test "x86-64-avx2-intel"
     run_dump_test "x86-64-avx-gather"
     run_dump_test "x86-64-avx-gather-intel"
+    run_dump_test "cvt-2si"
     run_dump_test "x86-64-avx512f"
     run_dump_test "x86-64-avx512f-intel"
     run_dump_test "x86-64-avx512f-opts"
--- a/gas/testsuite/gas/i386/ilp32/x86-64-simd-suffix.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-simd-suffix.d
@@ -60,15 +60,15 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f 2a 00          	cvtpi2pd \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	0f 2a 00             	cvtpi2ps \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	0f 2d 00             	cvtps2pi \(%rax\),%mm0
-[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f2 48 0f 2d 00       	cvtsd2siq \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f2 48 0f 2c 00       	cvttsd2siq \(%rax\),%rax
 [ 	]*[a-f0-9]+:	f2 0f 5a 00          	cvtsd2ss \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	f3 0f 5a 00          	cvtss2sd \(%rax\),%xmm0
-[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f3 48 0f 2d 00       	cvtss2siq \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f3 48 0f 2c 00       	cvttss2siq \(%rax\),%rax
 [ 	]*[a-f0-9]+:	f2 0f 5e 00          	divsd  \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	f3 0f 5e 00          	divss  \(%rax\),%xmm0
@@ -179,15 +179,15 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f 2a 00          	cvtpi2pd \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	0f 2a 00             	cvtpi2ps \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	0f 2d 00             	cvtps2pi \(%rax\),%mm0
-[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f2 48 0f 2d 00       	cvtsd2siq \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f2 48 0f 2c 00       	cvttsd2siq \(%rax\),%rax
 [ 	]*[a-f0-9]+:	f2 0f 5a 00          	cvtsd2ss \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	f3 0f 5a 00          	cvtss2sd \(%rax\),%xmm0
-[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f3 48 0f 2d 00       	cvtss2siq \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f3 48 0f 2c 00       	cvttss2siq \(%rax\),%rax
 [ 	]*[a-f0-9]+:	f2 0f 5e 00          	divsd  \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	f3 0f 5e 00          	divss  \(%rax\),%xmm0
--- a/gas/testsuite/gas/i386/simd-suffix.d
+++ b/gas/testsuite/gas/i386/simd-suffix.d
@@ -44,12 +44,12 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f 2a 00          	cvtpi2pd \(%eax\),%xmm0
 [ 	]*[a-f0-9]+:	0f 2a 00             	cvtpi2ps \(%eax\),%xmm0
 [ 	]*[a-f0-9]+:	0f 2d 00             	cvtps2pi \(%eax\),%mm0
-[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2si \(%eax\),%eax
-[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2sil \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2sil \(%eax\),%eax
 [ 	]*[a-f0-9]+:	f2 0f 5a 00          	cvtsd2ss \(%eax\),%xmm0
 [ 	]*[a-f0-9]+:	f3 0f 5a 00          	cvtss2sd \(%eax\),%xmm0
-[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2si \(%eax\),%eax
-[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2sil \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2sil \(%eax\),%eax
 [ 	]*[a-f0-9]+:	f2 0f 5e 00          	divsd  \(%eax\),%xmm0
 [ 	]*[a-f0-9]+:	f3 0f 5e 00          	divss  \(%eax\),%xmm0
 [ 	]*[a-f0-9]+:	f2 0f 5f 00          	maxsd  \(%eax\),%xmm0
@@ -137,12 +137,12 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f 2a 00          	cvtpi2pd \(%eax\),%xmm0
 [ 	]*[a-f0-9]+:	0f 2a 00             	cvtpi2ps \(%eax\),%xmm0
 [ 	]*[a-f0-9]+:	0f 2d 00             	cvtps2pi \(%eax\),%mm0
-[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2si \(%eax\),%eax
-[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2sil \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2sil \(%eax\),%eax
 [ 	]*[a-f0-9]+:	f2 0f 5a 00          	cvtsd2ss \(%eax\),%xmm0
 [ 	]*[a-f0-9]+:	f3 0f 5a 00          	cvtss2sd \(%eax\),%xmm0
-[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2si \(%eax\),%eax
-[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2si \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2sil \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2sil \(%eax\),%eax
 [ 	]*[a-f0-9]+:	f2 0f 5e 00          	divsd  \(%eax\),%xmm0
 [ 	]*[a-f0-9]+:	f3 0f 5e 00          	divss  \(%eax\),%xmm0
 [ 	]*[a-f0-9]+:	f2 0f 5f 00          	maxsd  \(%eax\),%xmm0
--- a/gas/testsuite/gas/i386/x86-64-simd-suffix.d
+++ b/gas/testsuite/gas/i386/x86-64-simd-suffix.d
@@ -60,15 +60,15 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f 2a 00          	cvtpi2pd \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	0f 2a 00             	cvtpi2ps \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	0f 2d 00             	cvtps2pi \(%rax\),%mm0
-[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f2 48 0f 2d 00       	cvtsd2siq \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f2 48 0f 2c 00       	cvttsd2siq \(%rax\),%rax
 [ 	]*[a-f0-9]+:	f2 0f 5a 00          	cvtsd2ss \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	f3 0f 5a 00          	cvtss2sd \(%rax\),%xmm0
-[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f3 48 0f 2d 00       	cvtss2siq \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f3 48 0f 2c 00       	cvttss2siq \(%rax\),%rax
 [ 	]*[a-f0-9]+:	f2 0f 5e 00          	divsd  \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	f3 0f 5e 00          	divss  \(%rax\),%xmm0
@@ -179,15 +179,15 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f 2a 00          	cvtpi2pd \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	0f 2a 00             	cvtpi2ps \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	0f 2d 00             	cvtps2pi \(%rax\),%mm0
-[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2d 00          	cvtsd2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f2 48 0f 2d 00       	cvtsd2siq \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 2c 00          	cvttsd2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f2 48 0f 2c 00       	cvttsd2siq \(%rax\),%rax
 [ 	]*[a-f0-9]+:	f2 0f 5a 00          	cvtsd2ss \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	f3 0f 5a 00          	cvtss2sd \(%rax\),%xmm0
-[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2d 00          	cvtss2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f3 48 0f 2d 00       	cvtss2siq \(%rax\),%rax
-[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2si \(%rax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f 2c 00          	cvttss2sil \(%rax\),%eax
 [ 	]*[a-f0-9]+:	f3 48 0f 2c 00       	cvttss2siq \(%rax\),%rax
 [ 	]*[a-f0-9]+:	f2 0f 5e 00          	divsd  \(%rax\),%xmm0
 [ 	]*[a-f0-9]+:	f3 0f 5e 00          	divss  \(%rax\),%xmm0
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -2536,8 +2536,7 @@ struct dis386 {
 	  prefix and behave as 'S' otherwise
    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
    'X' => print 's', 'd' depending on data16 prefix (for XMM)
-   'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
-	  suffix_always is true.
+   'Y' unused.
    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
    '!' => change condition from true to false or from false to true.
    '%' => add 1 upper case letter to the macro.
@@ -3925,17 +3924,17 @@ static const struct dis386 prefix_table[
   /* PREFIX_0F2C */
   {
     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
-    { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
+    { "cvttss2siS", { Gv, EXd }, PREFIX_OPCODE },
     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
-    { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
+    { "cvttsd2siS", { Gv, EXq }, PREFIX_OPCODE },
   },
 
   /* PREFIX_0F2D */
   {
     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
-    { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
+    { "cvtss2siS", { Gv, EXd }, PREFIX_OPCODE },
     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
-    { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
+    { "cvtsd2siS", { Gv, EXq }, PREFIX_OPCODE },
   },
 
   /* PREFIX_0F2E */
@@ -9547,26 +9546,26 @@ static const struct dis386 vex_len_table
 
   /* VEX_LEN_0F2C_P_1 */
   {
-    { "vcvttss2siY",	{ Gv, EXdScalar }, 0 },
-    { "vcvttss2siY",	{ Gv, EXdScalar }, 0 },
+    { "vcvttss2siS",	{ Gv, EXdScalar }, 0 },
+    { "vcvttss2siS",	{ Gv, EXdScalar }, 0 },
   },
 
   /* VEX_LEN_0F2C_P_3 */
   {
-    { "vcvttsd2siY",	{ Gv, EXqScalar }, 0 },
-    { "vcvttsd2siY",	{ Gv, EXqScalar }, 0 },
+    { "vcvttsd2siS",	{ Gv, EXqScalar }, 0 },
+    { "vcvttsd2siS",	{ Gv, EXqScalar }, 0 },
   },
 
   /* VEX_LEN_0F2D_P_1 */
   {
-    { "vcvtss2siY",	{ Gv, EXdScalar }, 0 },
-    { "vcvtss2siY",	{ Gv, EXdScalar }, 0 },
+    { "vcvtss2siS",	{ Gv, EXdScalar }, 0 },
+    { "vcvtss2siS",	{ Gv, EXdScalar }, 0 },
   },
 
   /* VEX_LEN_0F2D_P_3 */
   {
-    { "vcvtsd2siY",	{ Gv, EXqScalar }, 0 },
-    { "vcvtsd2siY",	{ Gv, EXqScalar }, 0 },
+    { "vcvtsd2siS",	{ Gv, EXqScalar }, 0 },
+    { "vcvtsd2siS",	{ Gv, EXqScalar }, 0 },
   },
 
   /* VEX_LEN_0F2E_P_0 */
@@ -14414,16 +14413,7 @@ case_S:
 	  break;
 	case 'Y':
 	  if (l == 0 && len == 1)
-	    {
-	      if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
-		break;
-	      if (rex & REX_W)
-		{
-		  USED_REX (REX_W);
-		  *obufp++ = 'q';
-		}
-	      break;
-	    }
+	    abort ();
 	  else
 	    {
 	      if (l != 1 || len != 2 || last[0] != 'X')
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -1011,16 +1011,16 @@ static const struct dis386 evex_table[][
   /* PREFIX_EVEX_0F2C */
   {
     { Bad_Opcode },
-    { "vcvttss2si",	{ Gdq, EXxmm_md, EXxEVexS }, 0 },
+    { "vcvttss2siS",	{ Gv, EXxmm_md, EXxEVexS }, 0 },
     { Bad_Opcode },
-    { "vcvttsd2si",	{ Gdq, EXxmm_mq, EXxEVexS }, 0 },
+    { "vcvttsd2siS",	{ Gv, EXxmm_mq, EXxEVexS }, 0 },
   },
   /* PREFIX_EVEX_0F2D */
   {
     { Bad_Opcode },
-    { "vcvtss2si",	{ Gdq, EXxmm_md, EXxEVexR }, 0 },
+    { "vcvtss2siS",	{ Gv, EXxmm_md, EXxEVexR }, 0 },
     { Bad_Opcode },
-    { "vcvtsd2si",	{ Gdq, EXxmm_mq, EXxEVexR }, 0 },
+    { "vcvtsd2siS",	{ Gv, EXxmm_mq, EXxEVexR }, 0 },
   },
   /* PREFIX_EVEX_0F2E */
   {
@@ -1317,16 +1317,16 @@ static const struct dis386 evex_table[][
   /* PREFIX_EVEX_0F78 */
   {
     { VEX_W_TABLE (EVEX_W_0F78_P_0) },
-    { "vcvttss2usi",	{ Gdq, EXxmm_md, EXxEVexS }, 0 },
+    { "vcvttss2usiS",	{ Gv, EXxmm_md, EXxEVexS }, 0 },
     { VEX_W_TABLE (EVEX_W_0F78_P_2) },
-    { "vcvttsd2usi",	{ Gdq, EXxmm_mq, EXxEVexS }, 0 },
+    { "vcvttsd2usiS",	{ Gv, EXxmm_mq, EXxEVexS }, 0 },
   },
   /* PREFIX_EVEX_0F79 */
   {
     { VEX_W_TABLE (EVEX_W_0F79_P_0) },
-    { "vcvtss2usi",	{ Gdq, EXxmm_md, EXxEVexR }, 0 },
+    { "vcvtss2usiS",	{ Gv, EXxmm_md, EXxEVexR }, 0 },
     { VEX_W_TABLE (EVEX_W_0F79_P_2) },
-    { "vcvtsd2usi",	{ Gdq, EXxmm_mq, EXxEVexR }, 0 },
+    { "vcvtsd2usiS",	{ Gv, EXxmm_mq, EXxEVexR }, 0 },
   },
   /* PREFIX_EVEX_0F7A */
   {
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3450,14 +3450,10 @@ vcvtps2ph, 3, 0x661D, None, 1, CpuAVX512
 vcvtps2ph, 4, 0x661D, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegYMM|RegMem }
 vcvtps2ph, 3, 0x661D, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, YMMword|Unspecified|BaseIndex }
 
-vcvtsd2si, 2, 0xF22D, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, Reg32 }
-vcvtsd2si, 3, 0xF22D, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg32 }
-vcvtsd2si, 2, 0xF22D, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, Reg64 }
-vcvtsd2si, 3, 0xF22D, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg64 }
-vcvtsd2usi, 2, 0xF279, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, Reg32 }
-vcvtsd2usi, 3, 0xF279, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg32 }
-vcvtsd2usi, 2, 0xF279, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, Reg64 }
-vcvtsd2usi, 3, 0xF279, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg64 }
+vcvtsd2si, 2, 0xF22D, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { RegXMM|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
+vcvtsd2si, 3, 0xF22D, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg32|Reg64 }
+vcvtsd2usi, 2, 0xF279, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { RegXMM|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
+vcvtsd2usi, 3, 0xF279, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg32|Reg64 }
 
 vcvtsd2ss, 3, 0xF25A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
 vcvtsd2ss, 4, 0xF25A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
@@ -3472,59 +3468,41 @@ vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX51
 vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
 
 vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Reg32, Imm8, RegXMM, RegXMM }
-vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32, RegXMM, RegXMM }
 vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
-vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
+vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg32|Reg64, Imm8, RegXMM, RegXMM }
+vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
 vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Reg32, Imm8, RegXMM, RegXMM }
-vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32, RegXMM, RegXMM }
 vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
-vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
+vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg32|Reg64, Imm8, RegXMM, RegXMM }
+vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
 
 vcvtss2sd, 3, 0xF35A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
 vcvtss2sd, 4, 0xF35A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
 
-vcvtss2si, 2, 0xF32D, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, Reg32 }
-vcvtss2si, 3, 0xF32D, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg32 }
-vcvtss2si, 2, 0xF32D, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, Reg64 }
-vcvtss2si, 3, 0xF32D, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg64 }
-vcvtss2usi, 2, 0xF379, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, Reg32 }
-vcvtss2usi, 3, 0xF379, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg32 }
-vcvtss2usi, 2, 0xF379, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, Reg64 }
-vcvtss2usi, 3, 0xF379, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg64 }
+vcvtss2si, 2, 0xF32D, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { RegXMM|Dword|Unspecified|BaseIndex, Reg32|Reg64 }
+vcvtss2si, 3, 0xF32D, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg32|Reg64 }
+vcvtss2usi, 2, 0xF379, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { RegXMM|Dword|Unspecified|BaseIndex, Reg32|Reg64 }
+vcvtss2usi, 3, 0xF379, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg32|Reg64 }
 
 vcvttpd2dq, 2, 0x66E6, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM }
 vcvttpd2dq, 3, 0x66E6, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegYMM }
-
 vcvttpd2udq, 2, 0x78, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM }
 vcvttpd2udq, 3, 0x78, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegYMM }
 
 vcvttps2dq, 2, 0xF35B, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM }
 vcvttps2dq, 3, 0xF35B, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
-
 vcvttps2udq, 2, 0x78, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM }
 vcvttps2udq, 3, 0x78, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
 
-vcvttsd2si, 2, 0xF22C, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, Reg32 }
-vcvttsd2si, 3, 0xF22C, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg32 }
-vcvttsd2si, 2, 0xF22C, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, Reg64 }
-vcvttsd2si, 3, 0xF22C, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg64 }
-vcvttsd2usi, 2, 0xF278, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, Reg32 }
-vcvttsd2usi, 3, 0xF278, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg32 }
-vcvttsd2usi, 2, 0xF278, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, Reg64 }
-vcvttsd2usi, 3, 0xF278, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg64 }
-
-vcvttss2si, 2, 0xF32C, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, Reg32 }
-vcvttss2si, 3, 0xF32C, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg32 }
-vcvttss2si, 2, 0xF32C, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, Reg64 }
-vcvttss2si, 3, 0xF32C, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg64 }
-vcvttss2usi, 2, 0xF378, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, Reg32 }
-vcvttss2usi, 3, 0xF378, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg32 }
-vcvttss2usi, 2, 0xF378, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, Reg64 }
-vcvttss2usi, 3, 0xF378, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg64 }
+vcvttsd2si, 2, 0xF22C, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { RegXMM|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
+vcvttsd2si, 3, 0xF22C, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg32|Reg64 }
+vcvttsd2usi, 2, 0xF278, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { RegXMM|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
+vcvttsd2usi, 3, 0xF278, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg32|Reg64 }
+
+vcvttss2si, 2, 0xF32C, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { RegXMM|Dword|Unspecified|BaseIndex, Reg32|Reg64 }
+vcvttss2si, 3, 0xF32C, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg32|Reg64 }
+vcvttss2usi, 2, 0xF378, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { RegXMM|Dword|Unspecified|BaseIndex, Reg32|Reg64 }
+vcvttss2usi, 3, 0xF378, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg32|Reg64 }
 
 vcvtudq2ps, 2, 0xF27A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex, RegZMM }
 vcvtudq2ps, 3, 0xF27A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM }




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