[PATCH v2] RISC-V: Add .insn support

[Kito Cheng]

This is v2 patch to support new directive, .insn for RISC-V assembler, it
able to write instruction with another form just like s/390's .insn
directive.

Main purpose of this directive is to make people easier to add new
instruction for experimentation without modify binutils, and it's much
usable than just use .word to encode instruction.

Changes since V1:
- Fix several typos.
-- Fix typo in document.
-- JAR -> JAL.
- Fix wrong value for NMADD and NMSUB.
- Allow 4 register operands for type R instruction.
- Allow to use FPR in all instruction format except base register operand.
- Remove "O2,CF3,d,Cj" for ci format.
- Fix wrong implementation for ciw and add update test case for that.
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