[PATCH] x86: Add NoXmmWordMem

[H.J. Lu]

On Tue, Jul 17, 2018 at 11:16 PM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 17.07.18 at 21:58, <hongjiu.lu@intel.com> wrote:
>> --- a/opcodes/i386-opc.tbl
>> +++ b/opcodes/i386-opc.tbl
>> @@ -5406,11 +5406,11 @@ vcvtpd2uqq, 2, 0x6679, None, 1,
>> CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=3|
>>  vcvtpd2uqq, 3, 0x6679, None, 1, CpuAVX512DQ,
>> Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|
>> No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM }
>>
>>  vcvtps2qq, 2, 0x667B, None, 1, CpuAVX512DQ,
>> Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|Broadcast|Disp8MemShift=5|IgnoreSiz
>> e|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
>> RegYMM|Dword|YMMword|Unspecified|BaseIndex, RegZMM }
>> -vcvtps2qq, 2, 0x667B, None, 1, CpuAVX512DQ|CpuAVX512VL,
>> Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast|Disp8MemShift=3|IgnoreSiz
>> e|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
>> RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
>> +vcvtps2qq, 2, 0x667B, None, 1, CpuAVX512DQ|CpuAVX512VL,
>> Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast|NoXmmWordMem|Disp8MemShif
>> t=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
>> RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
>>  vcvtps2qq, 2, 0x667B, None, 1, CpuAVX512DQ|CpuAVX512VL,
>> Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast|Disp8MemShift=4|IgnoreSiz
>> e|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
>> RegXMM|Dword|XMMword|Unspecified|BaseIndex, RegYMM }
>>  vcvtps2qq, 3, 0x667B, None, 1, CpuAVX512DQ,
>> Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|
>> No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegYMM, RegZMM }
>>  vcvtps2uqq, 2, 0x6679, None, 1, CpuAVX512DQ,
>> Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|Broadcast|Disp8MemShift=5|IgnoreSiz
>> e|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
>> RegYMM|Dword|YMMword|Unspecified|BaseIndex, RegZMM }
>> -vcvtps2uqq, 2, 0x6679, None, 1, CpuAVX512DQ|CpuAVX512VL,
>> Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast|Disp8MemShift=3|IgnoreSiz
>> e|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
>> RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
>> +vcvtps2uqq, 2, 0x6679, None, 1, CpuAVX512DQ|CpuAVX512VL,
>> Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast|NoXmmWordMem|Disp8MemShif
>> t=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
>> RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
>>  vcvtps2uqq, 2, 0x6679, None, 1, CpuAVX512DQ|CpuAVX512VL,
>> Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Broadcast|Disp8MemShift=4|IgnoreSiz
>> e|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
>> RegXMM|Dword|XMMword|Unspecified|BaseIndex, RegYMM }
>>  vcvtps2uqq, 3, 0x6679, None, 1, CpuAVX512DQ,
>> Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|
>> No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegYMM, RegZMM }
>
> Whichever adjustment it is that gets done in the end, vcvttps2{,u}qq
> will need the same.
>

I am checking in a patch to split them.

-- 
H.J.