[PATCH] x86/Intel: accept memory operand size specifiers for CET insns

[H.J. Lu]

On Tue, Jul 10, 2018 at 6:33 AM, Jan Beulich <JBeulich@suse.com> wrote:
> gas/
> 2018-07-10  Jan Beulich  <jbeulich@suse.com>
>
>         * testsuite/gas/i386/cet.s, testsuite/gas/i386/x86-64-cet.s:
>         Add Intel cases with operand size specifiers.
>         * testsuite/gas/i386/cet-intel.d, testsuite/gas/i386/cet.d,
>         testsuite/gas/i386/x86-64-cet-intel.d,
>         testsuite/gas/i386/x86-64-cet.d: Adjust expectations.
>
> opcodes/
> 2018-07-10  Jan Beulich  <jbeulich@suse.com>
>
>         * i386-opc.tbl (wrssd, wrussd): Add Dword.
>         (wrssq, wrussq): Add Qword.
>         * i386-tbl.h: Re-generate.
>

Should the disassembler be updated to add DWORD/QWORD?

-- 
H.J.