[PATCH][AArch64][binutils] Fix encodings for by element instructions.

[Tamar Christina]

Hi Jan,

Ah you're right... It seems scrolling through the Arm ARM I missed a section.

I've fixed these locally and will write a few tests to check for these for the future
and sent out the patch on Monday after double checking the list again.

Cheers,
Tamar

________________________________________
From: Jan Beulich <jbeulich@suse.com>
Sent: Sunday, July 8, 2018 10:00:48 AM
To: Tamar Christina
Cc: Marcus Shawcroft; nd; Richard Earnshaw; binutils@sourceware.org
Subject: Re: [PATCH][AArch64][binutils] Fix encodings for by element instructions.

>>> "Jan Beulich" <jbeulich@suse.com> 07/08/18 9:52 AM >>>
>>>> Tamar Christina <tamar.christina@arm.com> 06/27/18 4:36 PM >>>
>>Some instructions in Armv8-a place a limitation on FP16 registers that can be
>>used as the register from which to select an element from.
>>
>>e.g. fmla restricts Rm to 4 bits when using an FP16 register.  This restriction
>>does not apply for all instructions, e.g. fcmla does not have this restriction
>>>as it gets an extra bit from the M field.
>>
>>Unfortunately, this restriction to S_H was added for all _Em operands before,
>>meaning for a large number of instructions you couldn't use the full register
>>file.
>>
>>This fixes the issue by introducing a new operand _Em16 which applies this
>>restriction only when paired with S_H and leaves the _Em and the other
>>qualifiers for _Em16 unbounded (i.e. using the full 5 bit range).
>>
>>Also the patch updates all instructions that should be affected by this.
>
>I'm surprised that the patch updates smlal and smlal2, but not their sibling
>umlal and umlal2 - is that really correct?

Actually, smlsl/smlsl2 (and then also umlsl/umlsl2) as well, plus (at least)
smull/smull2 (and umull/umull2). Perhaps all insns with QL_ELEMENT_L /
QL_ELEMENT_L2 are affected?

Jan
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