[PATCH] RISC-V: Fix bug in prior addi/c.nop patch.

Jim Wilson jimw@sifive.com
Wed Jan 17 22:05:00 GMT 2018


This fixes a bug in my prior patch for recognizing an addi that can be emitted
as a compressed nop.  I forgot that '0' has special semantics, so I added a new
'z' operand type for this case.

I also took some time to set up a better test environment for my FSF binutils
work, using a tree with multiple git remotes so I can pull together the various
bits I need to test this properly.  This patch was tested with a binutils, gas,
and ld make check, and also a gcc make check, for the rv64gc/ilp32d linux
target.  There were no regressions.

Committed.

Jim

	gas/
	* config/tc-riscv.c (validate_riscv_insn) <'z'>: New.
	(riscv_ip) <'z'>: New.
	opcodes/
	* riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
---
 gas/config/tc-riscv.c | 10 ++++++++++
 opcodes/riscv-opc.c   |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index f60bea15c8..a84240db20 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -570,6 +570,7 @@ validate_riscv_insn (const struct riscv_opcode *opc)
       case 'p':	used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
       case 'q':	used_bits |= ENCODE_STYPE_IMM (-1U); break;
       case 'u':	used_bits |= ENCODE_UTYPE_IMM (-1U); break;
+      case 'z': break;
       case '[': break;
       case ']': break;
       case '0': break;
@@ -1712,6 +1713,15 @@ jump:
 		*imm_reloc = BFD_RELOC_RISCV_CALL;
 	      continue;
 
+	    case 'z':
+	      if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
+		  || imm_expr->X_op != O_constant
+		  || imm_expr->X_add_number != 0)
+		break;
+	      s = expr_end;
+	      imm_expr->X_op = O_absent;
+	      continue;
+
 	    default:
 	      as_fatal (_("internal error: bad argument type %c"), *args);
 	    }
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index a4e4b26598..4aeb55abb4 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -232,7 +232,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"bne",       "I",   "s,t,p",  MATCH_BNE, MASK_BNE, match_opcode, 0 },
 {"addi",      "C",   "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
 {"addi",      "C",   "d,CU,Cj",  MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
-{"addi",      "C",   "d,CU,0",    MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS },
+{"addi",      "C",   "d,CU,z",    MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS },
 {"addi",      "C",   "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
 {"addi",      "I",   "d,s,j",  MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
 {"add",       "C",   "d,CU,CV",  MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
-- 
2.14.1



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