smaller PLT entries for aarch64 (64-bit ARM)

Andreas Schwab schwab@linux-m68k.org
Mon Jan 15 22:29:00 GMT 2018


On Jan 15 2018, John Reiser <jreiser@bitwagon.com> wrote:

> Most of the PLT entries (Program Linkage Table) that I see on aarch64
> (64-bit ARM) contain code like (from binutils-gdb commit origin/master
> e09efd5931daf7eede1f4da46313a1aaadd4dbfa of Mon Jan 8 00:00:33 2018 +0000):
>
> ===== binutils/bfd/elfnn-aarch64.c near line 299
>   0x11, 0x02, 0x40, 0xf9,       /* ldr x17, [x16, PLTGOT + n * 8] */
>   0x10, 0x02, 0x00, 0x91,       /* add x16, x16, :lo12:PLTGOT + n * 8  */
> =====
>
> but this can be implemented one instruction shorter as:
>   0x11, 0x0e, 0x41, 0xf8,       /* ldr x17, [x16, PLTGOT + n * 8]! */
> where the exclamation point '!' denotes a write-back of the entire
> effective address (including the displacement) into the base register.

The wback form limits the offset to [-256,255].

Andreas.

-- 
Andreas Schwab, schwab@linux-m68k.org
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