[PATCH 6/6] x86: fold RegEip/RegRip and RegEiz/RegRiz
Jan Beulich
JBeulich@suse.com
Thu Aug 2 06:52:00 GMT 2018
This allows to simplify the code in a number of places.
gas/
2018-08-02 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (build_modrm_byte): Use RegIP and RegIZ.
(output_disp): Use RegIP.
(i386_addressing_mode): Drop/replace uses of RegEip/RegEiz.
(parse_real_register): Use RegIZ.
* config/tc-i386-intel.c (i386_intel_simplify_register): Use
RegIZ.
* testsuite/gas/i386/x86-64-mpx-inval-2.l: Adjust expectations.
opcodes/
2018-08-02 Jan Beulich <jbeulich@suse.com>
* i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
(RegIP, RegIZ): Define.
* i386-reg.tbl: Adjust comments.
(rip): Use Qword instead of BaseIndex. Use RegIP.
(eip): Use Dword instead of BaseIndex. Use RegIP.
(riz): Add Qword. Use RegIZ.
(eiz): Add Dword. Use RegIZ.
* i386-tbl.h: Re-generate.
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -289,8 +289,7 @@ i386_intel_simplify_register (expression
&& (i386_regtab[reg_num].reg_type.bitfield.xmmword
|| i386_regtab[reg_num].reg_type.bitfield.ymmword
|| i386_regtab[reg_num].reg_type.bitfield.zmmword
- || i386_regtab[reg_num].reg_num == RegRiz
- || i386_regtab[reg_num].reg_num == RegEiz))
+ || i386_regtab[reg_num].reg_num == RegIZ))
intel_state.index = i386_regtab + reg_num;
else if (!intel_state.base && !intel_state.in_scale)
intel_state.base = i386_regtab + reg_num;
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -7139,8 +7139,7 @@ build_modrm_byte (void)
if (i.tm.opcode_modifier.vecsib)
{
- if (i.index_reg->reg_num == RegEiz
- || i.index_reg->reg_num == RegRiz)
+ if (i.index_reg->reg_num == RegIZ)
abort ();
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
@@ -7211,8 +7210,7 @@ build_modrm_byte (void)
else if (!i.tm.opcode_modifier.vecsib)
{
/* !i.base_reg && i.index_reg */
- if (i.index_reg->reg_num == RegEiz
- || i.index_reg->reg_num == RegRiz)
+ if (i.index_reg->reg_num == RegIZ)
i.sib.index = NO_INDEX_REGISTER;
else
i.sib.index = i.index_reg->reg_num;
@@ -7238,8 +7236,7 @@ build_modrm_byte (void)
}
}
/* RIP addressing for 64bit mode. */
- else if (i.base_reg->reg_num == RegRip ||
- i.base_reg->reg_num == RegEip)
+ else if (i.base_reg->reg_num == RegIP)
{
gas_assert (!i.tm.opcode_modifier.vecsib);
i.rm.regmem = NO_BASE_REGISTER;
@@ -7331,8 +7328,7 @@ build_modrm_byte (void)
}
else if (!i.tm.opcode_modifier.vecsib)
{
- if (i.index_reg->reg_num == RegEiz
- || i.index_reg->reg_num == RegRiz)
+ if (i.index_reg->reg_num == RegIZ)
i.sib.index = NO_INDEX_REGISTER;
else
i.sib.index = i.index_reg->reg_num;
@@ -8178,8 +8174,7 @@ output_disp (fragS *insn_start_frag, off
{
fixP->fx_tcbit = i.rex != 0;
if (i.base_reg
- && (i.base_reg->reg_num == RegRip
- || i.base_reg->reg_num == RegEip))
+ && (i.base_reg->reg_num == RegIP))
fixP->fx_tcbit2 = 1;
}
else
@@ -9280,9 +9275,7 @@ i386_addressing_mode (void)
if (addr_reg)
{
- if (addr_reg->reg_num == RegEip
- || addr_reg->reg_num == RegEiz
- || addr_reg->reg_type.bitfield.dword)
+ if (addr_reg->reg_type.bitfield.dword)
addr_mode = CODE_32BIT;
else if (flag_code != CODE_64BIT
&& addr_reg->reg_type.bitfield.word)
@@ -9392,21 +9385,18 @@ bad_address:
{
/* 32-bit/64-bit checks. */
if ((i.base_reg
- && (addr_mode == CODE_64BIT
- ? !i.base_reg->reg_type.bitfield.qword
- : !i.base_reg->reg_type.bitfield.dword)
- && (i.index_reg
- || (i.base_reg->reg_num
- != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
+ && ((addr_mode == CODE_64BIT
+ ? !i.base_reg->reg_type.bitfield.qword
+ : !i.base_reg->reg_type.bitfield.dword)
+ || (i.index_reg && i.base_reg->reg_num == RegIP)
+ || i.base_reg->reg_num == RegIZ))
|| (i.index_reg
&& !i.index_reg->reg_type.bitfield.xmmword
&& !i.index_reg->reg_type.bitfield.ymmword
&& !i.index_reg->reg_type.bitfield.zmmword
&& ((addr_mode == CODE_64BIT
- ? !(i.index_reg->reg_type.bitfield.qword
- || i.index_reg->reg_num == RegRiz)
- : !(i.index_reg->reg_type.bitfield.dword
- || i.index_reg->reg_num == RegEiz))
+ ? !i.index_reg->reg_type.bitfield.qword
+ : !i.index_reg->reg_type.bitfield.dword)
|| !i.index_reg->reg_type.bitfield.baseindex)))
goto bad_address;
@@ -9415,7 +9405,7 @@ bad_address:
|| (current_templates->start->base_opcode & ~1) == 0x0f1a)
{
/* They cannot use RIP-relative addressing. */
- if (i.base_reg && i.base_reg->reg_num == RegRip)
+ if (i.base_reg && i.base_reg->reg_num == RegIP)
{
as_bad (_("`%s' cannot be used here"), operand_string);
return 0;
@@ -10475,8 +10465,7 @@ parse_real_register (char *reg_string, c
return (const reg_entry *) NULL;
/* Don't allow fake index register unless allow_index_reg isn't 0. */
- if (!allow_index_reg
- && (r->reg_num == RegEiz || r->reg_num == RegRiz))
+ if (!allow_index_reg && r->reg_num == RegIZ)
return (const reg_entry *) NULL;
/* Upper 16 vector registers are only available with VREX in 64bit
--- a/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
+++ b/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
@@ -2,7 +2,7 @@
.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:8: Error: `\(%rip\)' cannot be used here
-.*:9: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:9: Error: .*
.*:12: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:13: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:15: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
@@ -23,16 +23,16 @@
.*:38: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:39: Warning: register scaling is being ignored here
.*:40: Error: `base\(%rip\)' cannot be used here
-.*:41: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:41: Error: .*
.*:44: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:45: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:46: Warning: register scaling is being ignored here
.*:47: Error: `base\(%rip\)' cannot be used here
-.*:48: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:48: Error: .*
.*:51: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:52: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:53: Error: `\[rip\]' cannot be used here
-.*:54: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:54: Error: .*
.*:55: Error: `\[rax\+rsp\]' is not a valid base/index expression
.*:58: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:59: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
@@ -54,13 +54,13 @@
.*:84: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:85: Warning: register scaling is being ignored here
.*:86: Error: `\[rip\+base\]' cannot be used here
-.*:87: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:87: Error: .*
.*:88: Error: `\[rax\+rsp\]' is not a valid base/index expression
.*:91: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:92: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
.*:93: Warning: register scaling is being ignored here
.*:94: Error: `\[rip\+base\]' cannot be used here
-.*:95: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
+.*:95: Error: .*
.*:96: Error: `\[rax\+rsp\]' is not a valid base/index expression
GAS LISTING .*
@@ -77,10 +77,7 @@ GAS LISTING .*
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C1903
[ ]*[1-9][0-9]*[ ]+bndmk \(%rip\), %bnd3
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk \(%eip\), %bnd2
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+15000000
-[ ]*[1-9][0-9]*[ ]+00
+[ ]*[1-9][0-9]*[ ]+bndmk \(%eip\), %bnd2
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1
@@ -122,12 +119,12 @@ GAS LISTING .*
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+09
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1B bndcn 0x3\(%ecx,%eax,1\), %bnd1
- GAS LISTING .*
-
-
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C0103
[ ]*[1-9][0-9]*[ ]+bndcn %ecx, %bnd1
+ GAS LISTING .*
+
+
[ ]*[1-9][0-9]*[ ]+bndcn %cx, %bnd1
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndstx
@@ -141,9 +138,7 @@ GAS LISTING .*
.* Warning: register scaling is being ignored here
[ ]*[1-9][0-9]*[ ]+47
[ ]*[1-9][0-9]*[ ]+bndstx %bnd3, base\(%rip\)
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B0D bndstx %bnd1, base\(%eip\)
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+[0-9A-F]+
+[ ]*[1-9][0-9]*[ ]+bndstx %bnd1, base\(%eip\)
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndldx
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A44 bndldx 0x3\(%eax,%ebx,1\), %bnd0
@@ -156,9 +151,7 @@ GAS LISTING .*
.* Warning: register scaling is being ignored here
[ ]*[1-9][0-9]*[ ]*B8
[ ]*[1-9][0-9]*[ ]*bndldx base\(%rip\), %bnd1
-[ ]*[1-9][0-9]*[ ]*\?\?\?\? 670F1A1D bndldx base\(%eip\), %bnd3
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+[0-9A-F]+
+[ ]*[1-9][0-9]*[ ]*bndldx base\(%eip\), %bnd3
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\.intel_syntax noprefix
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[eax\]
@@ -168,10 +161,7 @@ GAS LISTING .*
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C0203
[ ]*[1-9][0-9]*[ ]*bndmk bnd3, \[rip\]
-[ ]*[1-9][0-9]*[ ]*\?\?\?\? 67F30F1B bndmk bnd2, \[eip\]
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions.
-[ ]*[1-9][0-9]*[ ]*15000000
-[ ]*[1-9][0-9]*[ ]*00
+[ ]*[1-9][0-9]*[ ]*bndmk bnd2, \[eip\]
[ ]*[1-9][0-9]*[ ]+bndmk bnd2, \[rax\+rsp\]
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
@@ -182,9 +172,6 @@ GAS LISTING .*
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+4C0203
[ ]*[1-9][0-9]*[ ]+
- GAS LISTING .*
-
-
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1B bndmov \[eax\], bnd1
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
[ ]*[1-9][0-9]*[ ]+08
@@ -195,6 +182,9 @@ GAS LISTING .*
[ ]*[1-9][0-9]*[ ]+\#\#\# bndcl
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[eax\]
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
+ GAS LISTING .*
+
+
[ ]*[1-9][0-9]*[ ]+08
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[edx\+1\*eax\+0x3\]
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
@@ -234,17 +224,12 @@ GAS LISTING .*
.* Warning: register scaling is being ignored here
[ ]*[1-9][0-9]*[ ]+B8
[ ]*[1-9][0-9]*[ ]+bndstx \[rip\+base\], bnd1
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B1D bndstx \[eip\+base\], bnd3
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+[0-9A-F]+
+[ ]*[1-9][0-9]*[ ]+bndstx \[eip\+base\], bnd3
[ ]*[1-9][0-9]*[ ]+bndstx \[rax\+rsp\], bnd3
[ ]*[1-9][0-9]*[ ]+
[ ]*[1-9][0-9]*[ ]+\#\#\# bndldx
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A44 bndldx bnd0, \[eax\+ebx\*1\+0x3\]
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
- GAS LISTING .*
-
-
[ ]*[1-9][0-9]*[ ]+1803
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A14 bndldx bnd2, \[1\*ebx\+3\]
.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
@@ -254,8 +239,6 @@ GAS LISTING .*
.* Warning: register scaling is being ignored here
[ ]*[1-9][0-9]*[ ]+C7
[ ]*[1-9][0-9]*[ ]+bndldx bnd1, \[rip\+base\]
-[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A1D bndldx bnd3, \[eip\+base\]
-.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
-[ ]*[1-9][0-9]*[ ]+[0-9A-F]+
+[ ]*[1-9][0-9]*[ ]+bndldx bnd3, \[eip\+base\]
[ ]*[1-9][0-9]*[ ]+bndldx bnd3, \[rax\+rsp\]
#pass
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -897,11 +897,9 @@ typedef struct
#define RegRex64 0x2 /* Extended 8 bit register. */
#define RegVRex 0x4 /* Extended vector register. */
unsigned char reg_num;
-#define RegRip ((unsigned char ) ~0)
-#define RegEip (RegRip - 1)
+#define RegIP ((unsigned char ) ~0)
/* EIZ and RIZ are fake index registers. */
-#define RegEiz (RegEip - 1)
-#define RegRiz (RegEiz - 1)
+#define RegIZ (RegIP - 1)
/* FLAT is a fake segment register (Intel mode). */
#define RegFlat ((unsigned char) ~0)
signed char dw2_regnum[2];
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -283,14 +283,14 @@ bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
-// No type will make these registers rejected for all purposes except
+// No Reg will make these registers rejected for all purposes except
// for addressing. This saves creating one extra type for RIP/EIP.
-rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
-eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
-// No type will make these registers rejected for all purposes except
+rip, Qword, RegRex64, RegIP, Dw2Inval, 16
+eip, Dword, RegRex64, RegIP, 8, Dw2Inval
+// No Reg will make these registers rejected for all purposes except
// for addressing.
-riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
-eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
+riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
+eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
// fp regs.
st(0), FloatReg|Acc, 0, 0, 11, 33
st(1), FloatReg, 0, 1, 12, 34
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