[PATCH, GAS/ARM, ping] Fix Coprocessor instructions availability
Thomas Preudhomme
thomas.preudhomme@foss.arm.com
Mon Oct 30 17:06:00 GMT 2017
Ping?
Best regards,
Thomas
On 17/10/17 09:53, Thomas Preudhomme wrote:
> Hi Richard,
>
> Good point. I've updated the cover letter and the patch as follows:
>
> Hi,
>
> A few coprocessor instructions introduced in ARMv2 are currently
> accepted by GAS when targeting ARMv1 due to a typo in the code. This
> patch fixes the issue and introduce a more fine grained testing for
> coprocessor instructions availability. Coprocessor instructions are
> grouped as follows:
>
> * ARM coprocessor instructions introduced in ARMv2
> Includes: ldc, stc, mcr, mrc, cdp, ldcl, stcl
> Guarded by: ARM_EXT_V2
> Tests: copro-arm_v2plus-arm_v*.d
>
> * ARM coprocessor instructions introduced in ARMv5
> Includes: ldc2, ldc2l, stc2, stc2l, cdp2, mcr2, mrc2
> Guarded by: ARM_EXT_V5
> Tests: copro-arm_v5plus-arm_v*.d
>
> * ARM coprocessor instructions introduced in ARMv5TE
> Includes: mcrr, mrrc
> Guarded by: ARM_EXT_V5E
> Tests: copro-arm_v5teplus-arm_v*.d
>
> * ARM coprocessor instructions introduced in ARMv6
> Includes: mcrr2, mrrc2
> Guarded by: ARM_EXT_V6
> Tests: copro-arm_v6plus-arm_v*.d
>
> * Thumb coprocessor instructions introduced in ARMv6T2
> Includes: ldc, ldcl, stc, stcl, mcr, mrc, mcrr, mrrc, cdp, ldc2,
> ldc2l, stc2, stc2l, cdp2, mcr2, mrc2, mcrr2, mrrc2
> Guarded by: ARM_EXT_V6T2
> Tests: copro-thumb_v6t2plus-thumb_v*.d
>
> For each of these groups, at least 2 tests are performed:
> * instructions are not available in earlier architecture
> * instructions are available in architecture where they were introduced
> More tests need to be performed when instructions in a group span
> several assembly files.
>
> Note that an instruction in the original coprocessor testcase is
> changed to unified syntax to allow the testcase to be assembled for ARM
> and Thumb state. Correct processing of legacy syntax is covered in other
> testcases.
>
> ChangeLog entries are as follow:
>
> *** gas/ChangeLog ***
>
> 2017-07-11 Thomas Preud'homme <thomas.preudhomme@arm.com>
>
> * config/tc-arm.c (arm_ext_v2): Define to ARM_EXT_V2 feature bit.
> * testsuite/gas/arm/copro.s: Split into ...
> * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus.s: This while
> changing it to unified syntax and ...
> * testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus.s: this and ...
> * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus.s: This and ...
> * testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus.s: This.
> * testsuite/gas/arm/copro.d: Split into ...
> * testsuite/gas/arm/copro-arm_v2plus-arm_v2.d: This but target ARMv2
> and ...
> * testsuite/gas/arm/copro-arm_v5plus-arm_v5.d: this but target ARMv5
> and ...
> * testsuite/gas/arm/copro-arm_v5teplus-arm_v5te.d: This but target
> ARMv5TE and ...
> * testsuite/gas/arm/copro-arm_v6plus-arm_v6.d: This but target ARMv6.
> * testsuite/gas/arm/copro-arm_v2plus-arm_v1.d: New testcase.
> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-1.d: New testcase.
> * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus-unavail.l: Expected
> errors for the above two testcases.
> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d: New testcase.
> * testsuite/gas/arm/copro-arm_v5plus-arm_v4.d: New testcase.
> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-2.d: New testcase.
> * testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus-unavail.l:
> Expected errors for the above two testcases.
> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d: New testcase.
> * testsuite/gas/arm/copro-arm_v5teplus-arm_v5.d: New testcase.
> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-3.d: New testcase.
> * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus-unavail.l:
> Expected errors for the above two testcases.
> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-3.d: New testcase.
> * testsuite/gas/arm/copro-arm_v6plus-arm_v5te.d: New testcase.
> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-4.d: New testcase.
> * testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus-unavail.l:
> Expected errors for the above two testcases.
> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-4.d: New testcase.
>
> Tested against testsuite for arm-none-eabi targets without any
> regression.
>
> Is that ok for master?
>
> Best regards,
>
> Thomas
>
> On 10/07/17 15:02, Richard Earnshaw (lists) wrote:
>> On 10/07/17 14:24, Thomas Preudhomme wrote:
>>> Hi,
>>>
>>> Coprocessor instructions are currently accepted by GAS for a number of
>>> target architecture when they are actually not available. In particular,
>>> many coprocessor instructions are not available in ARMv8-A but are
>>> currently accepted. Similarly, many are not available in ARMv1 but are
>>> accepted for that architecture because of a typo in the ARMv2 feature
>>> bit definition.
>>>
>>> This patch changes availability of co-processor instructions to the
>>> following:
>>>
>>> * ARM coprocessor instructions introduced in ARMv2 available in ARMv8-A
>>> Includes: ldc, stc, mcr, mrc
>>> Guarded by: ARM_EXT_V2
>>> Tests: copro-arm_v2plus-arm_v*.d
>>>
>>> * ARM coprocessor instructions introduced in ARMv2 but not available in
>>> ARMv8-A
>>> Includes: cdp, ldcl, stcl
>>> Guarded by: ARM_EXT2_CP1X8
>>> Tests: copro-arm_v2_nov8a-arm_v*.d
>>>
>>> * ARM coprocessor instructions introduced in ARMv5 but not available in
>>> ARMv8-A
>>> Includes: ldc2, ldc2l, stc2, stc2l, cdp2, mcr2, mrc2
>>> Guarded by: ARM_EXT2_CP2X8
>>> Tests: copro-arm_v5_nov8a-arm_v*.d
>>>
>>> * ARM coprocessor instructions introduced in ARMv5TE available in
>>> ARMv8-A
>>> Includes: mcrr, mrrc
>>> Guarded by: ARM_EXT_V5E
>>> Tests: copro-arm_v5teplus-arm_v*.d
>>>
>>> * ARM coprocessor instructions introduced in ARMv6 but not available in
>>> ARMv8-A
>>> Includes: mcrr2, mrrc2
>>> Guarded by: ARM_EXT2_CP4X8
>>> Tests: copro-arm_v6_nov8a-arm_v*.d
>>>
>>> * Thumb coprocessor instructions introduced in ARMv6T2 available in
>>> ARMv8-A
>>> Includes: ldc, ldcl, stc, stcl, mcr, mrc, mcrr, mrrc
>>> Guarded by: ARM_EXT_V6T2
>>> Tests: copro-thumb_v6t2plus-thumb_v*.d
>>>
>>> * ARM coprocessor instructions introduced in ARMv6T2 but not available
>>> in ARMv8-A
>>> Includes: cdp, ldc2, ldc2l, stc2, stc2l, cdp2, mcr2, mrc2, mcrr2,
>>> mrrc2
>>> Guarded by: ARM_EXT2_CPTX8
>>> Tests: copro-thumb_v6t2_nov8a-thumb_v*.d
>>>
>>> For each of these groups, at least 3 tests are performed:
>>> * instructions are not available in earlier architecture
>>> * instructions are available in architecture where they were introduced
>>> * instructions are (not, depending on group) available in ARMv8-A
>>> More tests need to be performed when instructions in a group span
>>> several assembly files.
>>>
>>> Note that an instruction in the original coprocessor testcase is
>>> changed to unified syntax to allow the testcase to be assembled for ARM
>>> and Thumb state. Correct processing of legacy syntax is covered in other
>>> testcases.
>>>
>>
>> So what happens to code that uses the generic co-processor instructions
>> as deliberate aliases to the VFP ISA? This code needs to continue to
>> work as this is a generally used mechanism for controlled access to
>> these instructions from system code.
>>
>> R.
>>
>>> ChangeLog entries are as follow:
>>>
>>> *** include/ChangeLog ***
>>>
>>> 2017-06-30 Thomas Preud'homme <thomas.preudhomme@arm.com>
>>>
>>> * opcode/arm.h (ARM_EXT2_CP1X8, ARM_EXT2_CP2X8, ARM_EXT2_CP4X8,
>>> ARM_EXT2_CPTX8, ARM_AEXT2_V2, ARM_AEXT2_V3, ARM_AEXT2_V4, ARM_AEXT2_V5,
>>> ARM_AEXT2_V6, ARM_AEXT2_V6T2, ARM_AEXT2_V7): New feature bit macros.
>>> (ARM_AEXT2_V8AR, ARM_AEXT2_V8A, ARM_AEXT2_V8_1A,
>>> ARM_AEXT2_V8_2A, ARM_AEXT2_V8_3A, ARM_AEXT2_V8M, ARM_AEXT2_V8M_MAIN,
>>> ARM_AEXT2_V8M_MAIN_DSP, ARM_AEXT2_V8R): Move definitions after the
>>> above.
>>> (ARM_ARCH_V2, ARM_ARCH_V2S, ARM_ARCH_V3, ARM_ARCH_V3M, ARM_ARCH_V4xM,
>>> ARM_ARCH_V4, ARM_ARCH_V4TxM, ARM_ARCH_V4T, ARM_ARCH_V5xM, ARM_ARCH_V5,
>>> ARM_ARCH_V5TxM, ARM_ARCH_V5T, ARM_ARCH_V5TExP, ARM_ARCH_V5TE,
>>> ARM_ARCH_V5TEJ, ARM_ARCH_V6, ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6KZ,
>>> ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, ARM_ARCH_V6KZT2,
>>> ARM_ARCH_V6M, ARM_ARCH_V6SM, ARM_ARCH_V7, ARM_ARCH_V7A, ARM_ARCH_V7VE,
>>> ARM_ARCH_V7R, ARM_ARCH_V7M, ARM_ARCH_V7EM): Add feature bit for
>>> supported coprocessor instructions in corresponding architectures.
>>>
>>> *** gas/ChangeLog ***
>>>
>>> 2017-07-03 Thomas Preud'homme <thomas.preudhomme@arm.com>
>>>
>>> * config/tc-arm.c (arm_ext_v2): Define to ARM_EXT_V2 feature bit.
>>> (arm_ext_cp1x8, arm_ext_cp2x8, arm_ext_cp4x8, arm_ext_cptx8): Define
>>> feature sets.
>>> (insns): Guard ldc, stc, mcr and mrc by arm_ext_cptx8 for Thumb state.
>>> Guard cdp, ldcl and stcl by arm_ext_cp1x8 for ARM state and
>>> arm_ext_cptx8 for Thumb state. Guard ldc2, ldc2l, stc2, stc2l,
>>> cdp2, mcr2 and mrc2 by arm_ext_cp2x8 for ARM state and arm_ext_cptx8
>>> for Thumb state. Guard mcrr2 and mrrc2 by arm_ext_cp4x8 for ARM
>>> state and arm_ext_cptx8 for Thumb state.
>>> * testsuite/gas/arm/copro.s: Split into ...
>>> * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus.s: This while
>>> changing it to unified syntax and ...
>>> * testsuite/gas/arm/copro-arm_v2_nov8a-thumb_v6t2_nov8a.s: this and ...
>>> * testsuite/gas/arm/copro-arm_v5_nov8a-thumb_v6t2_nov8a.s: this and ...
>>> * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus.s: This and ...
>>> * testsuite/gas/arm/copro-arm_v6_nov8a-thumb_v6t2_nov8a.s: This.
>>> * testsuite/gas/arm/copro.d: Split into ...
>>> * testsuite/gas/arm/copro-arm_v2plus-arm_v2.d: This but target ARMv2
>>> and ...
>>> * testsuite/gas/arm/copro-arm_v2_nov8a-arm_v2.d: This but target ARMv2
>>> and ...
>>> * testsuite/gas/arm/copro-arm_v5_nov8a-arm_v5.d: this but target ARMv5
>>> and ...
>>> * testsuite/gas/arm/copro-arm_v5teplus-arm_v5te.d: This but target
>>> ARMv5TE and ...
>>> * testsuite/gas/arm/copro-arm_v6_nov8a-arm_v6.d: This but target ARMv6.
>>> * testsuite/gas/arm/copro-arm_v2plus-arm_v1.d: New testcase.
>>> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-1.d: New testcase.
>>> * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus-unavail.l: Expected
>>> errors for the above two testcases.
>>> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d: New testcase.
>>> * testsuite/gas/arm/copro-arm_v2plus-arm_v8a.d: New testcase.
>>> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v8a-1.d: New testcase.
>>> * testsuite/gas/arm/copro-arm_v2_nov8a-arm_v1.d: New testcase.
>>> * testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v4t-1.d: New testcase.
>>> * testsuite/gas/arm/copro-arm_v2_nov8a-arm_v8a.d: New testcase.
>>> * testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v8a-1.d: New testcase.
>>> * testsuite/gas/arm/copro-arm_v2_nov8a-thumb_v6t2_nov8a-unavail.l:
>>> Expected errors for the above four testcases.
>>> * testsuite/gas/arm/copro-arm_v5_nov8a-arm_v4.d: New testcase.
>>> * testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v4t-2.d: New testcase.
>>> * testsuite/gas/arm/copro-arm_v5_nov8a-arm_v8a.d: New testcase.
>>> * testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v8a-2.d: New testcase.
>>> * testsuite/gas/arm/copro-arm_v5_nov8a-thumb_v6t2_nov8a-unavail.l:
>>> Expected errors for the above four testcases.
>>> * testsuite/gas/arm/copro-arm_v5teplus-arm_v5.d: New testcase.
>>> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-2.d: New testcase.
>>> * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus-unavail.l:
>>> Expected errors for the above two testcases.
>>> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d: New testcase.
>>> * testsuite/gas/arm/copro-arm_v5teplus-arm_v8a.d: New testcase.
>>> * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v8a-2.d: New testcase.
>>> * testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v4t-3.d: New testcase.
>>> * testsuite/gas/arm/copro-arm_v6_nov8a-arm_v5te.d: New testcase.
>>> * testsuite/gas/arm/copro-arm_v6_nov8a-arm_v8a.d: New testcase.
>>> * testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v8a-3.d: New testcase.
>>> * testsuite/gas/arm/copro-arm_v6_nov8a-thumb_v6t2_nov8a-unavail.l:
>>> Expected errors for the above four testcases.
>>> * testsuite/gas/arm/copro-arm_v6_nov8a-arm_v6.d: New testcase.
>>> * testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v6t2-3.d: New
>>> testcase.
>>>
>>> Tested against testsuite for arm-none-eabi targets without any
>>> regression.
>>>
>>> Is that ok for master?
>>>
>>> Best regards,
>>>
>>> Thomas
>>>
>>> fix_coproc_insns_availability.patch
>>>
>>>
>>> diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
>>> index
>>> f1d8fd09d9007f9dc9bf8ed42e921d4817ae82f2..8b5323a783bc4cc1e4a041aab10e7f2e83d0e7d8
>>> 100644
>>> --- a/gas/config/tc-arm.c
>>> +++ b/gas/config/tc-arm.c
>>> @@ -173,12 +173,16 @@ static const arm_feature_set cpu_default = CPU_DEFAULT;
>>> #endif
>>> static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
>>> -static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
>>> +static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2);
>>> static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
>>> static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
>>> static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
>>> +static const arm_feature_set arm_ext_cp1x8 =
>>> + ARM_FEATURE_CORE_HIGH (ARM_EXT2_CP1X8);
>>> static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
>>> static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
>>> +static const arm_feature_set arm_ext_cp2x8 =
>>> + ARM_FEATURE_CORE_HIGH (ARM_EXT2_CP2X8);
>>> static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
>>> static const arm_feature_set arm_ext_v4t_5 =
>>> ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
>>> @@ -186,8 +190,12 @@ static const arm_feature_set arm_ext_v5t =
>>> ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
>>> static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
>>> static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW
>>> (ARM_EXT_V5ExP);
>>> static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
>>> +static const arm_feature_set arm_ext_cp4x8 =
>>> + ARM_FEATURE_CORE_HIGH (ARM_EXT2_CP4X8);
>>> static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
>>> static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
>>> +static const arm_feature_set arm_ext_cptx8 =
>>> + ARM_FEATURE_CORE_HIGH (ARM_EXT2_CPTX8);
>>> static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW
>>> (ARM_EXT_V6T2);
>>> static const arm_feature_set arm_ext_v6_notm =
>>> ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
>>> @@ -19452,11 +19460,8 @@ static const struct asm_opcode insns[] =
>>> C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
>>> /* Generic coprocessor instructions. */
>>> - TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b),
>>> cdp, cdp),
>>> TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> - TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> - TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),
>>> co_reg, co_reg),
>>> TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b),
>>> co_reg, co_reg),
>>> @@ -19489,6 +19494,16 @@ static const struct asm_opcode insns[] =
>>> CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc),
>>> mull),
>>> #undef ARM_VARIANT
>>> +#define ARM_VARIANT & arm_ext_cp1x8
>>> +#undef THUMB_VARIANT
>>> +#define THUMB_VARIANT & arm_ext_cptx8
>>> +
>>> + /* Generic coprocessor instructions. */
>>> + TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b),
>>> cdp, cdp),
>>> + TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> + TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> +
>>> +#undef ARM_VARIANT
>>> #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
>>> #undef THUMB_VARIANT
>>> #define THUMB_VARIANT & arm_ext_v4t
>>> @@ -19509,6 +19524,19 @@ static const struct asm_opcode insns[] =
>>> TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
>>> #undef ARM_VARIANT
>>> +#define ARM_VARIANT & arm_ext_cp2x8
>>> +#undef THUMB_VARIANT
>>> +#define THUMB_VARIANT & arm_ext_cptx8
>>> +
>>> + TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> + TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> + TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> + TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> + TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b),
>>> cdp, cdp),
>>> + TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),
>>> co_reg, co_reg),
>>> + TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),
>>> co_reg, co_reg),
>>> +
>>> +#undef ARM_VARIANT
>>> #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
>>> #undef THUMB_VARIANT
>>> #define THUMB_VARIANT & arm_ext_v5t
>>> @@ -19522,13 +19550,6 @@ static const struct asm_opcode insns[] =
>>> #define THUMB_VARIANT & arm_ext_v6t2
>>> TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm,
>>> t_clz),
>>> - TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> - TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> - TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> - TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC),
>>> lstc, lstc),
>>> - TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b),
>>> cdp, cdp),
>>> - TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),
>>> co_reg, co_reg),
>>> - TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),
>>> co_reg, co_reg),
>>> #undef ARM_VARIANT
>>> #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
>>> @@ -19602,8 +19623,10 @@ static const struct asm_opcode insns[] =
>>> TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex,
>>> t_ldrex),
>>> TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
>>> strex, t_strex),
>>> +#undef ARM_VARIANT
>>> +#define ARM_VARIANT & arm_ext_cp4x8
>>> #undef THUMB_VARIANT
>>> -#define THUMB_VARIANT & arm_ext_v6t2
>>> +#define THUMB_VARIANT & arm_ext_cptx8
>>> TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN),
>>> co_reg2c, co_reg2c),
>>> TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN),
>>> co_reg2c, co_reg2c),
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v2_nov8a-arm_v1.d
>>> b/gas/testsuite/gas/arm/copro-arm_v2_nov8a-arm_v1.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..33552eabc44de7c5c68e385a39b3bb87a86327fe
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v2_nov8a-arm_v1.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v2_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: No ARMv2 ARM CoProcessor Instructions on ARMv1 (2)
>>> +#as: -march=armv1 -EL
>>> +#error-output: copro-arm_v2_nov8a-thumb_v6t2_nov8a-unavail.l
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v2_nov8a-arm_v2.d
>>> b/gas/testsuite/gas/arm/copro-arm_v2_nov8a-arm_v2.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..30ecd07db14a627b07d3ea090d90b8aaf254f099
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v2_nov8a-arm_v2.d
>>> @@ -0,0 +1,19 @@
>>> +#source: copro-arm_v2_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: ARMv2 ARM CoProcessor Instructions (2)
>>> +#as: -march=armv2 -EL
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> ee421103 dvfs f1, f2, f3
>>> +0+004 <[^>]*> 0e3414a5 cfadddeq mvd1, mvd4, mvd5
>>> +0+008 <[^>]*> edd1e108 ldfp f6, \[r1, #32\]
>>> +0+00c <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64.*
>>> +0+010 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\]
>>> +0+014 <[^>]*> ecd43704 ldcl 7, cr3, \[r4\], \{4\}
>>> +0+018 <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\}
>>> +0+01c <[^>]*> ecd88cff ldcl 12, cr8, \[r8\], \{255\}.*
>>> +0+020 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\}.*
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v2_nov8a-arm_v8a.d
>>> b/gas/testsuite/gas/arm/copro-arm_v2_nov8a-arm_v8a.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..6f530d075fedbb001f8ee65563afc1d9522983c3
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v2_nov8a-arm_v8a.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v2_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: Forbidden ARMv2 ARM CoProcessor Instructions on ARMv8-A
>>> +#as: -march=armv8-a -EL
>>> +#error-output: copro-arm_v2_nov8a-thumb_v6t2_nov8a-unavail.l
>>> diff --git
>>> a/gas/testsuite/gas/arm/copro-arm_v2_nov8a-thumb_v6t2_nov8a-unavail.l
>>> b/gas/testsuite/gas/arm/copro-arm_v2_nov8a-thumb_v6t2_nov8a-unavail.l
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..7a4e36a11162c3670dc8fe6b46ad632f60aba16b
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v2_nov8a-thumb_v6t2_nov8a-unavail.l
>>> @@ -0,0 +1,10 @@
>>> +[^:]*: Assembler messages:
>>> +[^:]*:5: Error: selected processor does not support `cdp [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:6: Error: selected processor does not support `cdpeq [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:7: Error: selected processor does not support `ldcl [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:8: Error: selected processor does not support `ldclpl [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:9: Error: selected processor does not support `stcl [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:11: Error: selected processor does not support `ldcl [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:12: Error: selected processor does not support `stcl [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:14: Error: selected processor does not support `ldcl [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:15: Error: selected processor does not support `stcl [^']*' in
>>> (ARM|Thumb) mode
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v2_nov8a-thumb_v6t2_nov8a.s
>>> b/gas/testsuite/gas/arm/copro-arm_v2_nov8a-thumb_v6t2_nov8a.s
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..44a3ca318733bdfb56cb76487a222c8cb0b5017a
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v2_nov8a-thumb_v6t2_nov8a.s
>>> @@ -0,0 +1,15 @@
>>> +.syntax unified
>>> +.text
>>> +.align 0
>>> +foo:
>>> + cdp p1, 4, cr1, cr2, cr3
>>> + cdpeq 4, 3, c1, c4, cr5, 5
>>> + ldcl 1, cr14, [r1, #32]
>>> + ldclpl p7, c1, [r3], #64
>>> + stcl 3, cr15, [r0, #8]
>>> + @ The following patterns test Addressing Mode 5 "Unindexed"
>>> + ldcl 7, c3, [r4], {4}
>>> + stcl p8, c2, [r5], {5}
>>> + @ using '11' below results in an (invalid) Neon vldmia instruction.
>>> + ldcl 12, c8, [r8], {255}
>>> + stcl p12, c9, [r9], {254}
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v1.d
>>> b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v1.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..3c7f0fb640a311b96a21d4347e81b0329bbfe51b
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v1.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v2plus-thumb_v6t2plus.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: No ARMv2 ARM CoProcessor Instructions on ARMv1 (1)
>>> +#as: -march=armv1 -EL
>>> +#error-output: copro-arm_v2plus-thumb_v6t2plus-unavail.l
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d
>>> b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..e7558abac41801d4553f3e124b8f1d3bf26eabe9
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d
>>> @@ -0,0 +1,27 @@
>>> +#source: copro-arm_v2plus-thumb_v6t2plus.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: ARMv2 ARM CoProcessor Instructions (1)
>>> +#as: -march=armv2 -EL
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> ed939500 cfldr32 mvfx9, \[r3\]
>>> +0+004 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
>>> +0+008 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!.*
>>> +0+00c <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] ; .* <foo>
>>> +0+010 <[^>]*> ed830500 cfstr32 mvfx0, \[r3\]
>>> +0+014 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]!.*
>>> +0+018 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48.*
>>> +0+01c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] ; .* <bar>
>>> +0+020 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\}
>>> +0+024 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
>>> +0+028 <[^>]*> ee215711 mcr 7, 1, r5, cr1, cr1, \{0\}
>>> +0+02c <[^>]*> be228519 mcrlt 5, 1, r8, cr2, cr9, \{0\}
>>> +0+030 <[^>]*> ec907300 ldc 3, cr7, \[r0\], \{0\}
>>> +0+034 <[^>]*> ec816e01 stc 14, cr6, \[r1\], \{1\}
>>> +0+038 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
>>> +0+03c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
>>> +0+040 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v8a.d
>>> b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v8a.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..eff10359ae37cd3fb4ccd1ba7cbce9f3f5872b65
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v8a.d
>>> @@ -0,0 +1,27 @@
>>> +#source: copro-arm_v2plus-thumb_v6t2plus.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: Allowed ARMv2 ARM CoProcessor Instructions on ARMv8-A
>>> +#as: -march=armv8-a -EL
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> ed939500 cfldr32 mvfx9, \[r3\]
>>> +0+004 <[^>]*> e320f000 nop \{0\}
>>> +0+008 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!.*
>>> +0+00c <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] ; .* <foo>
>>> +0+010 <[^>]*> ed830500 cfstr32 mvfx0, \[r3\]
>>> +0+014 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]!.*
>>> +0+018 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48.*
>>> +0+01c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] ; .* <bar>
>>> +0+020 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\}
>>> +0+024 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
>>> +0+028 <[^>]*> ee215711 mcr 7, 1, r5, cr1, cr1, \{0\}
>>> +0+02c <[^>]*> be228519 mcrlt 5, 1, r8, cr2, cr9, \{0\}
>>> +0+030 <[^>]*> ec907300 ldc 3, cr7, \[r0\], \{0\}
>>> +0+034 <[^>]*> ec816e01 stc 14, cr6, \[r1\], \{1\}
>>> +0+038 <[^>]*> e320f000 nop \{0\}
>>> +0+03c <[^>]*> e320f000 nop \{0\}
>>> +0+040 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus-unavail.l
>>> b/gas/testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus-unavail.l
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..6444fc618ff0aa948a6964745e3fe70920bf94d8
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus-unavail.l
>>> @@ -0,0 +1,15 @@
>>> +[^:]*: Assembler messages:
>>> +[^:]*:4: Error: selected processor does not support `ldc [^.]*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:7: Error: selected processor does not support `ldcmi [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:8: Error: selected processor does not support `ldc [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:11: Error: selected processor does not support `stc [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:12: Error: selected processor does not support `stceq [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:13: Error: selected processor does not support `stccc [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:14: Error: selected processor does not support `stc [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:17: Error: selected processor does not support `mrc [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:18: Error: selected processor does not support `mrcge [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:20: Error: selected processor does not support `mcr [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:21: Error: selected processor does not support `mcrlt [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:24: Error: selected processor does not support `ldc [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:25: Error: selected processor does not support `stc [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:32: Error: selected processor does not support `mrcge [^']*' in
>>> (ARM|Thumb) mode
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus.s
>>> b/gas/testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus.s
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..33ab117b2a5d115137f23011bab091f5b4477cb0
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus.s
>>> @@ -0,0 +1,32 @@
>>> +.syntax unified
>>> +.text
>>> +.align 0
>>> + ldc 5, cr9, [r3]
>>> + # Extra instruction to allow foo to be 4-byte aligned in Thumb
>>> + nop
>>> + ldcmi 0, cr0, [r2, #1020]!
>>> + ldc p0, c8, foo
>>> +foo:
>>> +
>>> + stc 5, cr0, [r3]
>>> + stceq p4, cr12, [r2, #100]!
>>> + stccc p6, c8, [r4], #48
>>> + stc p1, c7, bar
>>> +bar:
>>> +
>>> + mrc 2, 3, r5, c1, c2
>>> + mrcge p4, 5, r15, cr1, cr2, 7
>>> +
>>> + mcr p7, 1, r5, cr1, cr1
>>> + mcrlt 5, 1, r8, cr2, cr9, 0
>>> +
>>> + @ The following patterns test Addressing Mode 5 "Unindexed"
>>> + ldc 3, c7, [r0], {0}
>>> + stc p14, c6, [r1], {1}
>>> +
>>> + # Extra instructions to allow for code alignment in arm-aout target.
>>> + nop
>>> + nop
>>> +
>>> + # UAL-syntax for MRC with APSR. Pre-UAL was PC
>>> + mrcge p4, 5, APSR_nzcv, cr1, cr2, 7
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v5_nov8a-arm_v4.d
>>> b/gas/testsuite/gas/arm/copro-arm_v5_nov8a-arm_v4.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..cd2de8279c47a427f90824536ab16379eb6b8997
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v5_nov8a-arm_v4.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v5_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: No ARMv5 ARM CoProcessor Instructions on ARMv4
>>> +#as: -march=armv4 -EL
>>> +#error-output: copro-arm_v5_nov8a-thumb_v6t2_nov8a-unavail.l
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v5_nov8a-arm_v5.d
>>> b/gas/testsuite/gas/arm/copro-arm_v5_nov8a-arm_v5.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..4aeae1c6c6a2c9e71d6d5e6413977806d1004e5b
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v5_nov8a-arm_v5.d
>>> @@ -0,0 +1,23 @@
>>> +#source: copro-arm_v5_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: ARMv5 ARM CoProcessor Instructions
>>> +#as: -march=armv5 -EL
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> fe421103 cdp2 1, 4, cr1, cr2, cr3, \{0\}
>>> +0+004 <[^>]*> fd939500 ldc2 5, cr9, \[r3\]
>>> +0+008 <[^>]*> fdd1e108 ldc2l 1, cr14, \[r1, #32\]
>>> +0+00c <[^>]*> fd1f8001 ldc2 0, cr8, \[pc, #-4\] ; .* <foo>
>>> +0+010 <[^>]*> fd830500 stc2 5, cr0, \[r3\]
>>> +0+014 <[^>]*> fdc0f302 stc2l 3, cr15, \[r0, #8\]
>>> +0+018 <[^>]*> fd0f7101 stc2 1, cr7, \[pc, #-4\] ; .* <bar>
>>> +0+01c <[^>]*> fe715212 mrc2 2, 3, r5, cr1, cr2, \{0\}
>>> +0+020 <[^>]*> fe215711 mcr2 7, 1, r5, cr1, cr1, \{0\}
>>> +0+024 <[^>]*> fc925502 ldc2 5, cr5, \[r2\], \{2\}
>>> +0+028 <[^>]*> fc834603 stc2 6, cr4, \[r3\], \{3\}
>>> +0+02c <[^>]*> fcd61c06 ldc2l 12, cr1, \[r6\], \{6\}
>>> +0+030 <[^>]*> fcc70c07 stc2l 12, cr0, \[r7\], \{7\}
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v5_nov8a-arm_v8a.d
>>> b/gas/testsuite/gas/arm/copro-arm_v5_nov8a-arm_v8a.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..7f301064b982e5e6eb41c4d1a78b46e4ca2433ef
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v5_nov8a-arm_v8a.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v5_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: Forbidden ARMv5 ARM CoProcessor Instructions on ARMv8-A
>>> +#as: -march=armv8-a -EL
>>> +#error-output: copro-arm_v5_nov8a-thumb_v6t2_nov8a-unavail.l
>>> diff --git
>>> a/gas/testsuite/gas/arm/copro-arm_v5_nov8a-thumb_v6t2_nov8a-unavail.l
>>> b/gas/testsuite/gas/arm/copro-arm_v5_nov8a-thumb_v6t2_nov8a-unavail.l
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..528bb8b691f3c4062394f6ec64a1b7958fcef671
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v5_nov8a-thumb_v6t2_nov8a-unavail.l
>>> @@ -0,0 +1,14 @@
>>> +[^:]*: Assembler messages:
>>> +[^:]*:3: Error: selected processor does not support `cdp2 [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:5: Error: selected processor does not support `ldc2 [^.]*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:6: Error: selected processor does not support `ldc2l [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:7: Error: selected processor does not support `ldc2 [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:10: Error: selected processor does not support `stc2 [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:11: Error: selected processor does not support `stc2l [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:12: Error: selected processor does not support `stc2 [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:15: Error: selected processor does not support `mrc2 [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:16: Error: selected processor does not support `mcr2 [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:20: Error: selected processor does not support `ldc2 [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:21: Error: selected processor does not support `stc2 [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:23: Error: selected processor does not support `ldc2l [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:24: Error: selected processor does not support `stc2l [^']*' in
>>> (ARM|Thumb) mode
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v5_nov8a-thumb_v6t2_nov8a.s
>>> b/gas/testsuite/gas/arm/copro-arm_v5_nov8a-thumb_v6t2_nov8a.s
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..249d4f04e1da2c9f8fb730cedf8c52dd5523c316
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v5_nov8a-thumb_v6t2_nov8a.s
>>> @@ -0,0 +1,24 @@
>>> +.text
>>> +.align 0
>>> + cdp2 p1, 4, cr1, cr2, cr3
>>> +
>>> + ldc2 5, cr9, [r3]
>>> + ldc2l 1, cr14, [r1, #32]
>>> + ldc2 p0, c8, foo
>>> +foo:
>>> +
>>> + stc2 5, cr0, [r3]
>>> + stc2l 3, cr15, [r0, #8]
>>> + stc2 p1, c7, bar
>>> +bar:
>>> +
>>> + mrc2 2, 3, r5, c1, c2
>>> + mcr2 p7, 1, r5, cr1, cr1
>>> +
>>> + @ The following patterns test Addressing Mode 5 "Unindexed"
>>> +
>>> + ldc2 5, c5, [r2], {2}
>>> + stc2 p6, c4, [r3], {3}
>>> + @ using '9, 10, 11' below results in an invalid ldc2l/stc2l
>>> instruction.
>>> + ldc2l 12, c1, [r6], {6}
>>> + stc2l p12, c0, [r7], {7}
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v5teplus-arm_v5.d
>>> b/gas/testsuite/gas/arm/copro-arm_v5teplus-arm_v5.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..d41c5737969367fb6d7e337583c087bb5c26831a
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v5teplus-arm_v5.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v5teplus-thumb_v6t2plus.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: No ARMv5TE ARM CoProcessor Instructions on ARMv5
>>> +#as: -march=armv5 -EL
>>> +#error-output: copro-arm_v5teplus-thumb_v6t2plus-unavail.l
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v5teplus-arm_v5te.d
>>> b/gas/testsuite/gas/arm/copro-arm_v5teplus-arm_v5te.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..6da7266455af790512419a1c14beb7533b17d93e
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v5teplus-arm_v5te.d
>>> @@ -0,0 +1,14 @@
>>> +#source: copro-arm_v5teplus-thumb_v6t2plus.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: ARMv5TE ARM CoProcessor Instructions
>>> +#as: -march=armv5te -EL
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> ec507d04 mrrc 13, 0, r7, r0, cr4
>>> +0+004 <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5
>>> +0+008 <[^>]*> ec507fff mrrc 15, 15, r7, r0, cr15
>>> +0+00c <[^>]*> ec407efe mcrr 14, 15, r7, r0, cr14
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v5teplus-arm_v8a.d
>>> b/gas/testsuite/gas/arm/copro-arm_v5teplus-arm_v8a.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..d01405865bfa1663d4ab6ae0ef47938ce84d9d4e
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v5teplus-arm_v8a.d
>>> @@ -0,0 +1,14 @@
>>> +#source: copro-arm_v5teplus-thumb_v6t2plus.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: Allowed ARMv5TE ARM CoProcessor Instructions on ARMv8-A
>>> +#as: -march=armv8-a -EL
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> ec507d04 mrrc 13, 0, r7, r0, cr4
>>> +0+004 <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5
>>> +0+008 <[^>]*> ec507fff mrrc 15, 15, r7, r0, cr15
>>> +0+00c <[^>]*> ec407efe mcrr 14, 15, r7, r0, cr14
>>> diff --git
>>> a/gas/testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus-unavail.l
>>> b/gas/testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus-unavail.l
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..0837a9cf1ef7098bab6770d235a28014db7f7370
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus-unavail.l
>>> @@ -0,0 +1,5 @@
>>> +[^:]*: Assembler messages:
>>> +[^:]*:4: Error: selected processor does not support `mrrc [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:5: Error: selected processor does not support `mcrr [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:6: Error: selected processor does not support `mrrc [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:7: Error: selected processor does not support `mcrr [^']*' in
>>> (ARM|Thumb) mode
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus.s
>>> b/gas/testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus.s
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..6cd2b1cfbf3daec78d68f7c58a27afa5cf807ff8
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus.s
>>> @@ -0,0 +1,7 @@
>>> +.text
>>> +.align 0
>>> +bar:
>>> + mrrc 13, 0, r7, r0, cr4
>>> + mcrr p14, 0, r7, r0, cr5
>>> + mrrc 15, 15, r7, r0, cr15
>>> + mcrr p14, 15, r7, r0, cr14
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v6_nov8a-arm_v5te.d
>>> b/gas/testsuite/gas/arm/copro-arm_v6_nov8a-arm_v5te.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..549f33309d33822a6ded68d2d923bb0ccc6593ce
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v6_nov8a-arm_v5te.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v6_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: No ARMv6 ARM CoProcessor Instructions on ARMv5TE
>>> +#as: -march=armv5te -EL
>>> +#error-output: copro-arm_v6_nov8a-thumb_v6t2_nov8a-unavail.l
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v6_nov8a-arm_v6.d
>>> b/gas/testsuite/gas/arm/copro-arm_v6_nov8a-arm_v6.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..c97c768372a066236c9bac6987d0d6a3d7157b70
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v6_nov8a-arm_v6.d
>>> @@ -0,0 +1,14 @@
>>> +#source: copro-arm_v6_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: ARMv6 ARM CoProcessor Instructions
>>> +#as: -march=armv6 -EL
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> fc507d04 mrrc2 13, 0, r7, r0, cr4
>>> +0+004 <[^>]*> fc407e05 mcrr2 14, 0, r7, r0, cr5
>>> +0+008 <[^>]*> fc507fff mrrc2 15, 15, r7, r0, cr15
>>> +0+00c <[^>]*> fc407efe mcrr2 14, 15, r7, r0, cr14
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v6_nov8a-arm_v8a.d
>>> b/gas/testsuite/gas/arm/copro-arm_v6_nov8a-arm_v8a.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..074fcce7bcf7a624f9966e3f7e175a8c8e366afd
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v6_nov8a-arm_v8a.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v6_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: Forbidden ARM ARMv6 CoProcessor Instructions on ARMv8-A
>>> +#as: -march=armv8-a -EL
>>> +#error-output: copro-arm_v6_nov8a-thumb_v6t2_nov8a-unavail.l
>>> diff --git
>>> a/gas/testsuite/gas/arm/copro-arm_v6_nov8a-thumb_v6t2_nov8a-unavail.l
>>> b/gas/testsuite/gas/arm/copro-arm_v6_nov8a-thumb_v6t2_nov8a-unavail.l
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..0f0a40ba67f7777601d98388f4a86393d494bb14
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v6_nov8a-thumb_v6t2_nov8a-unavail.l
>>> @@ -0,0 +1,5 @@
>>> +[^:]*: Assembler messages:
>>> +[^:]*:4: Error: selected processor does not support `mrrc2 [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:5: Error: selected processor does not support `mcrr2 [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:6: Error: selected processor does not support `mrrc2 [^']*' in
>>> (ARM|Thumb) mode
>>> +[^:]*:7: Error: selected processor does not support `mcrr2 [^']*' in
>>> (ARM|Thumb) mode
>>> diff --git a/gas/testsuite/gas/arm/copro-arm_v6_nov8a-thumb_v6t2_nov8a.s
>>> b/gas/testsuite/gas/arm/copro-arm_v6_nov8a-thumb_v6t2_nov8a.s
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..d6afb5f1bba43e36f5b039060a14a2511a566eef
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-arm_v6_nov8a-thumb_v6t2_nov8a.s
>>> @@ -0,0 +1,7 @@
>>> +.text
>>> +.align 0
>>> +bar:
>>> + mrrc2 13, 0, r7, r0, cr4
>>> + mcrr2 p14, 0, r7, r0, cr5
>>> + mrrc2 15, 15, r7, r0, cr15
>>> + mcrr2 p14, 15, r7, r0, cr14
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v4t-1.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v4t-1.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..2d1fec072d80e105194df9cd2d5c7a1cb0c1c47c
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v4t-1.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v2_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: No ARMv6T2 Thumb CoProcessor Instructions on ARMv4T (2)
>>> +#as: -march=armv4t -mthumb -mimplicit-it=always -EL
>>> +#error-output: copro-arm_v2_nov8a-thumb_v6t2_nov8a-unavail.l
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v4t-2.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v4t-2.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..66586dd80e8bc5d6102abe7ad5f2101cefc17038
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v4t-2.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v5_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: No ARMv6T2 Thumb CoProcessor Instructions on ARMv4T (3)
>>> +#as: -march=armv4t -mthumb -EL
>>> +#error-output: copro-arm_v5_nov8a-thumb_v6t2_nov8a-unavail.l
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v4t-3.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v4t-3.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..bd99d6c747b5d4b0ff2d377d6c387320e967cef9
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v4t-3.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v6_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: No ARMv6T2 Thumb CoProcessor Instructions on ARMv4T (5)
>>> +#as: -march=armv4t -mthumb -EL
>>> +#error-output: copro-arm_v6_nov8a-thumb_v6t2_nov8a-unavail.l
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v6t2-1.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v6t2-1.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..5d8bca34a0f00d41eb0254be403f25ed4f9088ce
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v6t2-1.d
>>> @@ -0,0 +1,22 @@
>>> +#source: copro-arm_v2_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: ARMv6T2 Thumb CoProcessor Instructions (2)
>>> +#as: -march=armv6t2 -mthumb -mimplicit-it=always -EL
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> ee42 1103 dvfs f1, f2, f3
>>> +0+004 <[^>]*> [^ ]* it eq
>>> +0+006 <[^>]*> ee34 14a5 cfadddeq mvd1, mvd4, mvd5
>>> +0+00a <[^>]*> edd1 e108 ldfp f6, \[r1, #32\]
>>> +0+00e <[^>]*> [^ ]* it pl
>>> +0+010 <[^>]*> ecf3 1710 ldclpl 7, cr1, \[r3\], #64.*
>>> +0+014 <[^>]*> edc0 f302 stcl 3, cr15, \[r0, #8\]
>>> +0+018 <[^>]*> ecd4 3704 ldcl 7, cr3, \[r4\], \{4\}
>>> +0+01c <[^>]*> ecc5 2805 stcl 8, cr2, \[r5\], \{5\}
>>> +0+020 <[^>]*> ecd8 8cff ldcl 12, cr8, \[r8\], \{255\}.*
>>> +0+024 <[^>]*> ecc9 9cfe stcl 12, cr9, \[r9\], \{254\}.*
>>> +#...
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v6t2-2.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v6t2-2.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..41bf97c889ceb30f2f3fa3cbb3fa4a4f79bf3cde
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v6t2-2.d
>>> @@ -0,0 +1,23 @@
>>> +#source: copro-arm_v5_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: ARMv6T2 Thumb CoProcessor Instructions (3)
>>> +#as: -march=armv6t2 -mthumb -EL
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> fe42 1103 cdp2 1, 4, cr1, cr2, cr3, \{0\}
>>> +0+004 <[^>]*> fd93 9500 ldc2 5, cr9, \[r3\]
>>> +0+008 <[^>]*> fdd1 e108 ldc2l 1, cr14, \[r1, #32\]
>>> +0+00c <[^>]*> fd9f 8000 ldc2 0, cr8, \[pc\] ; .* <foo>
>>> +0+010 <[^>]*> fd83 0500 stc2 5, cr0, \[r3\]
>>> +0+014 <[^>]*> fdc0 f302 stc2l 3, cr15, \[r0, #8\]
>>> +0+018 <[^>]*> fd8f 7100 stc2 1, cr7, \[pc\] ; .* <bar>
>>> +0+01c <[^>]*> fe71 5212 mrc2 2, 3, r5, cr1, cr2, \{0\}
>>> +0+020 <[^>]*> fe21 5711 mcr2 7, 1, r5, cr1, cr1, \{0\}
>>> +0+024 <[^>]*> fc92 5502 ldc2 5, cr5, \[r2\], \{2\}
>>> +0+028 <[^>]*> fc83 4603 stc2 6, cr4, \[r3\], \{3\}
>>> +0+02c <[^>]*> fcd6 1c06 ldc2l 12, cr1, \[r6\], \{6\}
>>> +0+030 <[^>]*> fcc7 0c07 stc2l 12, cr0, \[r7\], \{7\}
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v6t2-3.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v6t2-3.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..015f496adafa55083906a3985802ab73de15a564
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v6t2-3.d
>>> @@ -0,0 +1,14 @@
>>> +#source: copro-arm_v6_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: ARMv6T2 Thumb CoProcessor Instructions (5)
>>> +#as: -march=armv6t2 -mthumb -EL
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> fc50 7d04 mrrc2 13, 0, r7, r0, cr4
>>> +0+004 <[^>]*> fc40 7e05 mcrr2 14, 0, r7, r0, cr5
>>> +0+008 <[^>]*> fc50 7fff mrrc2 15, 15, r7, r0, cr15
>>> +0+00c <[^>]*> fc40 7efe mcrr2 14, 15, r7, r0, cr14
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v8a-1.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v8a-1.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..4d829669864897e21ad6e7367debf78d3f90a3b4
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v8a-1.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v2_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: Forbidden ARMv6T2 CoProcessor Instructions on ARMv8-A (1)
>>> +#as: -march=armv8-a -mthumb -mimplicit-it=always -EL
>>> +#error-output: copro-arm_v2_nov8a-thumb_v6t2_nov8a-unavail.l
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v8a-2.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v8a-2.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..5eed42340922a665238d1755b3fbc7c370238f7d
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v8a-2.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v5_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: Forbidden ARMv6T2 Thumb CoProcessor Instructions on ARMv8-A (2)
>>> +#as: -march=armv8-a -mthumb -EL
>>> +#error-output: copro-arm_v5_nov8a-thumb_v6t2_nov8a-unavail.l
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v8a-3.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v8a-3.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..38c7f0da91121ce3a1e424a4a0ebca7283c3f476
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2_nov8a-thumb_v8a-3.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v6_nov8a-thumb_v6t2_nov8a.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: Forbidden ARMv6T2 Thumb CoProcessor Instructions on ARMv8-A
>>> +#as: -march=armv8-a -mthumb -EL
>>> +#error-output: copro-arm_v6_nov8a-thumb_v6t2_nov8a-unavail.l
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-1.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-1.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..e7d528bfa522d48f081a2292cb1b1b3764546d44
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-1.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v2plus-thumb_v6t2plus.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: No ARMv6T2 Thumb CoProcessor Instructions on ARMv4T (1)
>>> +#as: -march=armv4t -mthumb -EL
>>> +#error-output: copro-arm_v2plus-thumb_v6t2plus-unavail.l
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-2.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-2.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..2fb0be0c33c2433d64de6c0fae1033714e25d278
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-2.d
>>> @@ -0,0 +1,5 @@
>>> +#source: copro-arm_v5teplus-thumb_v6t2plus.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: No ARMv6T2 Thumb CoProcessor Instructions on ARMv4T (3)
>>> +#as: -march=armv4t -mthumb -EL
>>> +#error-output: copro-arm_v5teplus-thumb_v6t2plus-unavail.l
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..a375b31b5fbea76d04a0317a6a2e9b08857115af
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d
>>> @@ -0,0 +1,34 @@
>>> +#source: copro-arm_v2plus-thumb_v6t2plus.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: ARMv6T2 Thumb CoProcessor Instructions (1)
>>> +#as: -march=armv6t2 -mthumb -mimplicit-it=always -EL
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> ed93 9500 cfldr32 mvfx9, \[r3\]
>>> +0+004 <[^>]*> bf00 nop
>>> +0+006 <[^>]*> [^ ]* it mi
>>> +0+008 <[^>]*> edb2 00ff ldcmi 0, cr0, \[r2, #1020\]!.*
>>> +0+00c <[^>]*> ed9f 8000 ldc 0, cr8, \[pc] ; .* <foo>
>>> +0+010 <[^>]*> ed83 0500 cfstr32 mvfx0, \[r3\]
>>> +0+014 <[^>]*> [^ ]* it eq
>>> +0+016 <[^>]*> eda2 c419 cfstrseq mvf12, \[r2, #100\]!.*
>>> +0+01a <[^>]*> [^ ]* it cc
>>> +0+01c <[^>]*> eca4 860c stccc 6, cr8, \[r4\], #48.*
>>> +0+020 <[^>]*> ed8f 7100 stfs f7, \[pc\] ; .* <bar>
>>> +0+024 <[^>]*> ee71 5212 mrc 2, 3, r5, cr1, cr2, \{0\}
>>> +0+028 <[^>]*> [^ ]* it ge
>>> +0+02a <[^>]*> eeb1 f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
>>> +0+02e <[^>]*> ee21 5711 mcr 7, 1, r5, cr1, cr1, \{0\}
>>> +0+032 <[^>]*> [^ ]* it lt
>>> +0+034 <[^>]*> ee22 8519 mcrlt 5, 1, r8, cr2, cr9, \{0\}
>>> +0+038 <[^>]*> ec90 7300 ldc 3, cr7, \[r0\], \{0\}
>>> +0+03c <[^>]*> ec81 6e01 stc 14, cr6, \[r1\], \{1\}
>>> +0+040 <[^>]*> bf00 nop
>>> +0+042 <[^>]*> bf00 nop
>>> +0+044 <[^>]*> [^ ]* it ge
>>> +0+046 <[^>]*> eeb1 f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
>>> +#...
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..0e864d9df4516e2bafd038a04628bef159f84bf8
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d
>>> @@ -0,0 +1,14 @@
>>> +#source: copro-arm_v5teplus-thumb_v6t2plus.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: ARMv6T2 Thumb CoProcessor Instructions (4)
>>> +#as: -march=armv6t2 -mthumb -EL
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> ec50 7d04 mrrc 13, 0, r7, r0, cr4
>>> +0+004 <[^>]*> ec40 7e05 mcrr 14, 0, r7, r0, cr5
>>> +0+008 <[^>]*> ec50 7fff mrrc 15, 15, r7, r0, cr15
>>> +0+00c <[^>]*> ec40 7efe mcrr 14, 15, r7, r0, cr14
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v8a-1.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v8a-1.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..d7c9909ad6af0298cba67f00d6c229c995301969
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v8a-1.d
>>> @@ -0,0 +1,35 @@
>>> +#source: copro-arm_v2plus-thumb_v6t2plus.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: Allowed ARMv6T2 Thumb CoProcessor Instructions on ARMv8-A (1)
>>> +#as: -march=armv8-a -mthumb -mimplicit-it=always -EL
>>> +#warning: IT blocks containing 32-bit Thumb instructions are deprecated in
>>> ARMv8
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> ed93 9500 cfldr32 mvfx9, \[r3\]
>>> +0+004 <[^>]*> bf00 nop
>>> +0+006 <[^>]*> [^ ]* it mi
>>> +0+008 <[^>]*> edb2 00ff ldcmi 0, cr0, \[r2, #1020\]!.*
>>> +0+00c <[^>]*> ed9f 8000 ldc 0, cr8, \[pc] ; .* <foo>
>>> +0+010 <[^>]*> ed83 0500 cfstr32 mvfx0, \[r3\]
>>> +0+014 <[^>]*> [^ ]* it eq
>>> +0+016 <[^>]*> eda2 c419 cfstrseq mvf12, \[r2, #100\]!.*
>>> +0+01a <[^>]*> [^ ]* it cc
>>> +0+01c <[^>]*> eca4 860c stccc 6, cr8, \[r4\], #48.*
>>> +0+020 <[^>]*> ed8f 7100 stfs f7, \[pc\] ; .* <bar>
>>> +0+024 <[^>]*> ee71 5212 mrc 2, 3, r5, cr1, cr2, \{0\}
>>> +0+028 <[^>]*> [^ ]* it ge
>>> +0+02a <[^>]*> eeb1 f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
>>> +0+02e <[^>]*> ee21 5711 mcr 7, 1, r5, cr1, cr1, \{0\}
>>> +0+032 <[^>]*> [^ ]* it lt
>>> +0+034 <[^>]*> ee22 8519 mcrlt 5, 1, r8, cr2, cr9, \{0\}
>>> +0+038 <[^>]*> ec90 7300 ldc 3, cr7, \[r0\], \{0\}
>>> +0+03c <[^>]*> ec81 6e01 stc 14, cr6, \[r1\], \{1\}
>>> +0+040 <[^>]*> bf00 nop
>>> +0+042 <[^>]*> bf00 nop
>>> +0+044 <[^>]*> [^ ]* it ge
>>> +0+046 <[^>]*> eeb1 f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
>>> +#...
>>> diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v8a-2.d
>>> b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v8a-2.d
>>> new file mode 100644
>>> index
>>> 0000000000000000000000000000000000000000..fedca06734607253b5cc22a79fbe15b072e7dad1
>>>
>>> --- /dev/null
>>> +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v8a-2.d
>>> @@ -0,0 +1,14 @@
>>> +#source: copro-arm_v5teplus-thumb_v6t2plus.s
>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>> +#name: Allowed ARMv6T2 Thumb CoProcessor Instructions on ARMv8-A (2)
>>> +#as: -march=armv8-a -mthumb -EL
>>> +
>>> +# Test the standard ARM co-processor instructions:
>>> +
>>> +.*: +file format .*arm.*
>>> +
>>> +Disassembly of section .text:
>>> +0+000 <[^>]*> ec50 7d04 mrrc 13, 0, r7, r0, cr4
>>> +0+004 <[^>]*> ec40 7e05 mcrr 14, 0, r7, r0, cr5
>>> +0+008 <[^>]*> ec50 7fff mrrc 15, 15, r7, r0, cr15
>>> +0+00c <[^>]*> ec40 7efe mcrr 14, 15, r7, r0, cr14
>>> diff --git a/gas/testsuite/gas/arm/copro.d b/gas/testsuite/gas/arm/copro.d
>>> deleted file mode 100644
>>> index
>>> e9ed2ccb6f9055bba6ce76aa2ae10dc3e34c3192..0000000000000000000000000000000000000000
>>>
>>> --- a/gas/testsuite/gas/arm/copro.d
>>> +++ /dev/null
>>> @@ -1,42 +0,0 @@
>>> -#objdump: -dr --prefix-addresses --show-raw-insn
>>> -#name: ARM CoProcessor Instructions
>>> -#as: -march=armv5te -EL
>>> -
>>> -# Test the standard ARM co-processor instructions:
>>> -
>>> -.*: +file format .*arm.*
>>> -
>>> -Disassembly of section .text:
>>> -0+000 <[^>]*> ee421103 dvfs f1, f2, f3
>>> -0+004 <[^>]*> 0e3414a5 cfadddeq mvd1, mvd4, mvd5
>>> -0+008 <[^>]*> ed939500 cfldr32 mvfx9, \[r3\]
>>> -0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\]
>>> -0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!.*
>>> -0+014 <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64.*
>>> -0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] ; .* <foo>
>>> -0+01c <[^>]*> ed830500 cfstr32 mvfx0, \[r3\]
>>> -0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\]
>>> -0+024 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]!.*
>>> -0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48.*
>>> -0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] ; .* <bar>
>>> -0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\}
>>> -0+034 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
>>> -0+038 <[^>]*> ee215711 mcr 7, 1, r5, cr1, cr1, \{0\}
>>> -0+03c <[^>]*> be228519 mcrlt 5, 1, r8, cr2, cr9, \{0\}
>>> -0+040 <[^>]*> ec907300 ldc 3, cr7, \[r0\], \{0\}
>>> -0+044 <[^>]*> ec816e01 stc 14, cr6, \[r1\], \{1\}
>>> -0+048 <[^>]*> fc925502 ldc2 5, cr5, \[r2\], \{2\}
>>> -0+04c <[^>]*> fc834603 stc2 6, cr4, \[r3\], \{3\}
>>> -0+050 <[^>]*> ecd43704 ldcl 7, cr3, \[r4\], \{4\}
>>> -0+054 <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\}
>>> -0+058 <[^>]*> fcd61c06 ldc2l 12, cr1, \[r6\], \{6\}
>>> -0+05c <[^>]*> fcc70c07 stc2l 12, cr0, \[r7\], \{7\}
>>> -0+060 <[^>]*> ecd88cff ldcl 12, cr8, \[r8\], \{255\}.*
>>> -0+064 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\}.*
>>> -0+068 <[^>]*> ec507d04 mrrc 13, 0, r7, r0, cr4
>>> -0+06c <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5
>>> -0+070 <[^>]*> ec507fff mrrc 15, 15, r7, r0, cr15
>>> -0+074 <[^>]*> ec407efe mcrr 14, 15, r7, r0, cr14
>>> -0+078 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
>>> -0+07c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
>>> -0+080 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
>>> diff --git a/gas/testsuite/gas/arm/copro.s b/gas/testsuite/gas/arm/copro.s
>>> deleted file mode 100644
>>> index
>>> 53533d48c208399d00048526bef272c4d2daaea4..0000000000000000000000000000000000000000
>>>
>>> --- a/gas/testsuite/gas/arm/copro.s
>>> +++ /dev/null
>>> @@ -1,50 +0,0 @@
>>> -.text
>>> -.align 0
>>> - cdp p1, 4, cr1, cr2, cr3
>>> - cdpeq 4, 3, c1, c4, cr5, 5
>>> -
>>> - ldc 5, cr9, [r3]
>>> - ldcl 1, cr14, [r1, #32]
>>> - ldcmi 0, cr0, [r2, #1020]!
>>> - ldcpll p7, c1, [r3], #64
>>> - ldc p0, c8, foo
>>> -foo:
>>> -
>>> - stc 5, cr0, [r3]
>>> - stcl 3, cr15, [r0, #8]
>>> - stceq p4, cr12, [r2, #100]!
>>> - stccc p6, c8, [r4], #48
>>> - stc p1, c7, bar
>>> -bar:
>>> -
>>> - mrc 2, 3, r5, c1, c2
>>> - mrcge p4, 5, r15, cr1, cr2, 7
>>> -
>>> - mcr p7, 1, r5, cr1, cr1
>>> - mcrlt 5, 1, r8, cr2, cr9, 0
>>> -
>>> - @ The following patterns test Addressing Mode 5 "Unindexed"
>>> -
>>> - ldc 3, c7, [r0], {0}
>>> - stc p14, c6, [r1], {1}
>>> - ldc2 5, c5, [r2], {2}
>>> - stc2 p6, c4, [r3], {3}
>>> - ldcl 7, c3, [r4], {4}
>>> - stcl p8, c2, [r5], {5}
>>> - @ using '9, 10, 11' below results in an invalid ldc2l/stc2l
>>> instruction.
>>> - ldc2l 12, c1, [r6], {6}
>>> - stc2l p12, c0, [r7], {7}
>>> - @ using '11' below results in an (invalid) Neon vldmia instruction.
>>> - ldcl 12, c8, [r8], {255}
>>> - stcl p12, c9, [r9], {254}
>>> - mrrc 13, 0, r7, r0, cr4
>>> - mcrr p14, 0, r7, r0, cr5
>>> - mrrc 15, 15, r7, r0, cr15
>>> - mcrr p14, 15, r7, r0, cr14
>>> -
>>> - # Extra instructions to allow for code alignment in arm-aout target.
>>> - nop
>>> - nop
>>> -
>>> - # UAL-syntax for MRC with APSR. Pre-UAL was PC
>>> - mrcge p4, 5, APSR_nzcv, cr1, cr2, 7
>>> diff --git a/include/opcode/arm.h b/include/opcode/arm.h
>>> index
>>> e11ac7c40bc3495888fbc502eef070320e30a92a..872de76b7b842d643fb716cff27ae04abac5f1d2
>>> 100644
>>> --- a/include/opcode/arm.h
>>> +++ b/include/opcode/arm.h
>>> @@ -66,6 +66,14 @@
>>> #define ARM_EXT2_RAS 0x00000080 /* RAS extension. */
>>> #define ARM_EXT2_V8_3A 0x00000100 /* ARM V8.3A. */
>>> #define ARM_EXT2_V8A 0x00000200 /* ARMv8-A. */
>>> +#define ARM_EXT2_CP1X8 0x00000400 /* Coprocessor instructions in ARMv2
>>> + but not ARMv8-A. */
>>> +#define ARM_EXT2_CP2X8 0x00000800 /* Coprocessor instructions in ARMv5
>>> + but not ARMv8-A. */
>>> +#define ARM_EXT2_CP4X8 0x00001000 /* Coprocessor instructions in ARMv6
>>> + but not ARMv8-A. */
>>> +#define ARM_EXT2_CPTX8 0x00002000 /* Thumb Coprocessor instructions in
>>> + ARMv6T2 but not ARMv8-A. */
>>> /* Co-processor space extensions. */
>>> #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
>>> @@ -151,19 +159,30 @@
>>> #define ARM_AEXT_V8A \
>>> (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \
>>> | ARM_EXT_VIRT | ARM_EXT_V8)
>>> -#define ARM_AEXT2_V8AR (ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS)
>>> -#define ARM_AEXT2_V8A (ARM_AEXT2_V8AR | ARM_EXT2_V8A)
>>> -#define ARM_AEXT2_V8_1A (ARM_AEXT2_V8A | ARM_EXT2_PAN)
>>> -#define ARM_AEXT2_V8_2A (ARM_AEXT2_V8_1A | ARM_EXT2_V8_2A | ARM_EXT2_RAS)
>>> -#define ARM_AEXT2_V8_3A (ARM_AEXT2_V8_2A | ARM_EXT2_V8_3A)
>>> #define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM | ARM_EXT_DIV)
>>> #define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M
>>> #define ARM_AEXT_V8M_MAIN_DSP ARM_AEXT_V7EM
>>> -#define ARM_AEXT2_V8M (ARM_EXT2_V8M | ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M)
>>> -#define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M | ARM_EXT2_V8M_MAIN)
>>> -#define ARM_AEXT2_V8M_MAIN_DSP ARM_AEXT2_V8M_MAIN
>>> #define ARM_AEXT_V8R ARM_AEXT_V8A
>>> -#define ARM_AEXT2_V8R ARM_AEXT2_V8AR
>>> +
>>> +#define ARM_AEXT2_V2 ARM_EXT2_CP1X8
>>> +#define ARM_AEXT2_V3 ARM_AEXT2_V2
>>> +#define ARM_AEXT2_V4 ARM_AEXT2_V3
>>> +#define ARM_AEXT2_V5 (ARM_AEXT2_V4 | ARM_EXT2_CP2X8)
>>> +#define ARM_AEXT2_V6 (ARM_AEXT2_V5 | ARM_EXT2_CP4X8)
>>> +#define ARM_AEXT2_V6T2 (ARM_AEXT2_V6 | ARM_EXT2_CPTX8 \
>>> + | ARM_EXT2_V6T2_V8M)
>>> +#define ARM_AEXT2_V7 ARM_AEXT2_V6T2
>>> +#define ARM_AEXT2_V8AR (ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS)
>>> +#define ARM_AEXT2_V8A (ARM_AEXT2_V8AR | ARM_EXT2_V8A)
>>> +#define ARM_AEXT2_V8_1A (ARM_AEXT2_V8A | ARM_EXT2_PAN)
>>> +#define ARM_AEXT2_V8_2A (ARM_AEXT2_V8_1A | ARM_EXT2_V8_2A \
>>> + | ARM_EXT2_RAS)
>>> +#define ARM_AEXT2_V8_3A (ARM_AEXT2_V8_2A | ARM_EXT2_V8_3A)
>>> +#define ARM_AEXT2_V8M (ARM_AEXT2_V6T2 | ARM_EXT2_V8M \
>>> + | ARM_EXT2_ATOMICS)
>>> +#define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M | ARM_EXT2_V8M_MAIN)
>>> +#define ARM_AEXT2_V8M_MAIN_DSP ARM_AEXT2_V8M_MAIN
>>> +#define ARM_AEXT2_V8R ARM_AEXT2_V8AR
>>> /* Processors with specific extensions in the co-processor space. */
>>> #define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
>>> @@ -244,37 +263,37 @@
>>> #define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK)
>>> #define ARM_ARCH_V1 ARM_FEATURE_CORE_LOW (ARM_AEXT_V1)
>>> -#define ARM_ARCH_V2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V2)
>>> -#define ARM_ARCH_V2S ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S)
>>> -#define ARM_ARCH_V3 ARM_FEATURE_CORE_LOW (ARM_AEXT_V3)
>>> -#define ARM_ARCH_V3M ARM_FEATURE_CORE_LOW (ARM_AEXT_V3M)
>>> -#define ARM_ARCH_V4xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4xM)
>>> -#define ARM_ARCH_V4 ARM_FEATURE_CORE_LOW (ARM_AEXT_V4)
>>> -#define ARM_ARCH_V4TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4TxM)
>>> -#define ARM_ARCH_V4T ARM_FEATURE_CORE_LOW (ARM_AEXT_V4T)
>>> -#define ARM_ARCH_V5xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5xM)
>>> -#define ARM_ARCH_V5 ARM_FEATURE_CORE_LOW (ARM_AEXT_V5)
>>> -#define ARM_ARCH_V5TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TxM)
>>> -#define ARM_ARCH_V5T ARM_FEATURE_CORE_LOW (ARM_AEXT_V5T)
>>> -#define ARM_ARCH_V5TExP ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TExP)
>>> -#define ARM_ARCH_V5TE ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TE)
>>> -#define ARM_ARCH_V5TEJ ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TEJ)
>>> -#define ARM_ARCH_V6 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6)
>>> -#define ARM_ARCH_V6K ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K)
>>> -#define ARM_ARCH_V6Z ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z)
>>> -#define ARM_ARCH_V6KZ ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZ)
>>> -#define ARM_ARCH_V6T2 ARM_FEATURE_CORE (ARM_AEXT_V6T2, ARM_EXT2_V6T2_V8M)
>>> -#define ARM_ARCH_V6KT2 ARM_FEATURE_CORE (ARM_AEXT_V6KT2, ARM_EXT2_V6T2_V8M)
>>> -#define ARM_ARCH_V6ZT2 ARM_FEATURE_CORE (ARM_AEXT_V6ZT2, ARM_EXT2_V6T2_V8M)
>>> -#define ARM_ARCH_V6KZT2 ARM_FEATURE_CORE (ARM_AEXT_V6KZT2,
>>> ARM_EXT2_V6T2_V8M)
>>> -#define ARM_ARCH_V6M ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M)
>>> -#define ARM_ARCH_V6SM ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM)
>>> -#define ARM_ARCH_V7 ARM_FEATURE_CORE (ARM_AEXT_V7, ARM_EXT2_V6T2_V8M)
>>> -#define ARM_ARCH_V7A ARM_FEATURE_CORE (ARM_AEXT_V7A, ARM_EXT2_V6T2_V8M)
>>> -#define ARM_ARCH_V7VE ARM_FEATURE_CORE (ARM_AEXT_V7VE, ARM_EXT2_V6T2_V8M)
>>> -#define ARM_ARCH_V7R ARM_FEATURE_CORE (ARM_AEXT_V7R, ARM_EXT2_V6T2_V8M)
>>> -#define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_EXT2_V6T2_V8M)
>>> -#define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M)
>>> +#define ARM_ARCH_V2 ARM_FEATURE_CORE (ARM_AEXT_V2, ARM_AEXT2_V2)
>>> +#define ARM_ARCH_V2S ARM_FEATURE_CORE (ARM_AEXT_V2S, ARM_AEXT2_V2)
>>> +#define ARM_ARCH_V3 ARM_FEATURE_CORE (ARM_AEXT_V3, ARM_AEXT2_V3)
>>> +#define ARM_ARCH_V3M ARM_FEATURE_CORE (ARM_AEXT_V3M, ARM_AEXT2_V3)
>>> +#define ARM_ARCH_V4xM ARM_FEATURE_CORE (ARM_AEXT_V4xM, ARM_AEXT2_V4)
>>> +#define ARM_ARCH_V4 ARM_FEATURE_CORE (ARM_AEXT_V4, ARM_AEXT2_V4)
>>> +#define ARM_ARCH_V4TxM ARM_FEATURE_CORE (ARM_AEXT_V4TxM, ARM_AEXT2_V4)
>>> +#define ARM_ARCH_V4T ARM_FEATURE_CORE (ARM_AEXT_V4T, ARM_AEXT2_V4)
>>> +#define ARM_ARCH_V5xM ARM_FEATURE_CORE (ARM_AEXT_V5xM, ARM_AEXT2_V5)
>>> +#define ARM_ARCH_V5 ARM_FEATURE_CORE (ARM_AEXT_V5, ARM_AEXT2_V5)
>>> +#define ARM_ARCH_V5TxM ARM_FEATURE_CORE (ARM_AEXT_V5TxM, ARM_AEXT2_V5)
>>> +#define ARM_ARCH_V5T ARM_FEATURE_CORE (ARM_AEXT_V5T, ARM_AEXT2_V5)
>>> +#define ARM_ARCH_V5TExP ARM_FEATURE_CORE (ARM_AEXT_V5TExP, ARM_AEXT2_V5)
>>> +#define ARM_ARCH_V5TE ARM_FEATURE_CORE (ARM_AEXT_V5TE, ARM_AEXT2_V5)
>>> +#define ARM_ARCH_V5TEJ ARM_FEATURE_CORE (ARM_AEXT_V5TEJ, ARM_AEXT2_V5)
>>> +#define ARM_ARCH_V6 ARM_FEATURE_CORE (ARM_AEXT_V6, ARM_AEXT2_V6)
>>> +#define ARM_ARCH_V6K ARM_FEATURE_CORE (ARM_AEXT_V6K, ARM_AEXT2_V6)
>>> +#define ARM_ARCH_V6Z ARM_FEATURE_CORE (ARM_AEXT_V6Z, ARM_AEXT2_V6)
>>> +#define ARM_ARCH_V6KZ ARM_FEATURE_CORE (ARM_AEXT_V6KZ, ARM_AEXT2_V6)
>>> +#define ARM_ARCH_V6T2 ARM_FEATURE_CORE (ARM_AEXT_V6T2, ARM_AEXT2_V6T2)
>>> +#define ARM_ARCH_V6KT2 ARM_FEATURE_CORE (ARM_AEXT_V6KT2, ARM_AEXT2_V6T2)
>>> +#define ARM_ARCH_V6ZT2 ARM_FEATURE_CORE (ARM_AEXT_V6ZT2, ARM_AEXT2_V6T2)
>>> +#define ARM_ARCH_V6KZT2 ARM_FEATURE_CORE (ARM_AEXT_V6KZT2, ARM_AEXT2_V6T2)
>>> +#define ARM_ARCH_V6M ARM_FEATURE_CORE (ARM_AEXT_V6M, ARM_AEXT2_V6)
>>> +#define ARM_ARCH_V6SM ARM_FEATURE_CORE (ARM_AEXT_V6SM, ARM_AEXT2_V6)
>>> +#define ARM_ARCH_V7 ARM_FEATURE_CORE (ARM_AEXT_V7, ARM_AEXT2_V7)
>>> +#define ARM_ARCH_V7A ARM_FEATURE_CORE (ARM_AEXT_V7A, ARM_AEXT2_V7)
>>> +#define ARM_ARCH_V7VE ARM_FEATURE_CORE (ARM_AEXT_V7VE, ARM_AEXT2_V7)
>>> +#define ARM_ARCH_V7R ARM_FEATURE_CORE (ARM_AEXT_V7R, ARM_AEXT2_V7)
>>> +#define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_AEXT2_V7)
>>> +#define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_AEXT2_V7)
>>> #define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A)
>>> #define ARM_ARCH_V8A_CRC ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, \
>>> CRC_EXT_ARMV8)
>>>
>>
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