[PATCH 2/6] Enable Intel GFNI instructions

[Jan Beulich]

>>> On 21.11.17 at 19:55, <hjl.tools@gmail.com> wrote:
> On Tue, Nov 21, 2017 at 7:03 AM, Tsimbalist, Igor V
> <igor.v.tsimbalist@intel.com> wrote:
>>> -----Original Message-----
>>> From: Jan Beulich [mailto:JBeulich@suse.com]
>>> Sent: Monday, November 20, 2017 9:09 AM
>>> To: Tsimbalist, Igor V <igor.v.tsimbalist@intel.com>
>>> Cc: Lu, Hongjiu <hongjiu.lu@intel.com>; binutils@sourceware.org 
>>> Subject: Re: [PATCH 2/6] Enable Intel GFNI instructions
>>>
>>> >>> On 21.10.17 at 11:17, <igor.v.tsimbalist@intel.com> wrote:
>>> >+// GFNI + AVX
>>> >+
>>> >+vgf2p8affineinvqb, 4, 0x66cf, None, 1, CpuAVX|CpuGFNI,
>>> Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No
>>> _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,
>>> Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM
>>> , RegXMM, RegXMM }
>>> >+vgf2p8affineinvqb, 4, 0x66cf, None, 1, CpuAVX|CpuGFNI,
>>> Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|
>>> No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,
>>> Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM,
>>> RegYMM, RegYMM }
>>> >+
>>> >+vgf2p8affineqb, 4, 0x66ce, None, 1, CpuAVX|CpuGFNI,
>>> Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No
>>> _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,
>>> Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM
>>> , RegXMM, RegXMM }
>>> >+vgf2p8affineqb, 4, 0x66ce, None, 1, CpuAVX|CpuGFNI,
>>> Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|
>>> No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,
>>> Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM,
>>> RegYMM, RegYMM }
>>> >+
>>> >+vgf2p8mulb, 3, 0x66cf, None, 1, CpuAVX|CpuGFNI,
>>> Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No
>>> _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
>>> RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S
>>> |Vec_Disp8, RegXMM, RegXMM }
>>> >+vgf2p8mulb, 3, 0x66cf, None, 1, CpuAVX|CpuGFNI,
>>> Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|
>>> No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
>>> RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S
>>> |Vec_Disp8, RegYMM, RegYMM }
>>>
>>> These being AVX flavors, there shouldn't be any Vec_Disp8 here.
>>
>> Attached is a patch to fix this. Ok for trunk?
>>
> 
> 2 comments:
> 
> 1. Do you also need to remove Vec_Disp8 from CpuGFNI|CpuAVX512VL vgf2p8mulb?

No - they (properly) have non-zero Disp8MemShift. Byte element
AVX-512 instructions using byte granular Disp8 scaling is specific
to vcompressb / vexpandb. All others scale by vector rather than
element size.

Jan

> 2.  ChangeLog should say
> 
> i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
> 
> -- 
> H.J.