[PATCH 3/3] x86: ignore high register select bit(s) in 32- and 16-bit modes

H.J. Lu hjl.tools@gmail.com
Tue Nov 14 12:43:00 GMT 2017


On Mon, Nov 13, 2017 at 11:32 PM, Jan Beulich <JBeulich@suse.com> wrote:
> While commits 9889cbb14e ("Check invalid mask registers") and
> abfcb414b9 ("X86: Ignore REX_B bit for 32-bit XOP instructions") went a
> bit into the right direction, this wasn't quite enough:
> - VEX.vvvv has its high bit ignored
> - EVEX.vvvv has its high bit ignored together with EVEX.v'
> - the high bits of {,E}VEX.vvvv should not be prematurely zapped, to
>   allow proper checking of them when the fields has to hold al ones
> - when the high bits of an immediate specify a register, bit 7 is
>   ignored
>
> gas/
> 2017-11-14  Jan Beulich  <jbeulich@suse.com>
>
>         * testsuite/gas/i386/noextreg.{s,d}: New.
>         * testsuite/gas/i386/i386.exp: Run new test.
>
> opcodes/
> 2017-11-14  Jan Beulich  <jbeulich@suse.com>
>
>         (get_valid_dis386): Never flag bad opcode when
>         vex.register_specifier is beyond 7. Always store all four
>         bits of it. Move 16-/32-bit override in EVEX handling after
>         all to be overridden bits have been set.
>         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
>         Use rex to determine GPR register set.
>         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
>         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
>
> --- 2017-11-10.orig/gas/testsuite/gas/i386/i386.exp     2017-11-10 08:33:58.850459503 +0100
> +++ 2017-11-10/gas/testsuite/gas/i386/i386.exp  2017-11-13 17:55:34.632165025 +0100
> @@ -182,6 +182,7 @@ if [expr ([istarget "i*86-*-*"] ||  [ist
>      run_dump_test "noavx-4"
>      run_list_test "noavx512-1" "-al"
>      run_list_test "noavx512-2" "-al"
> +    run_dump_test "noextreg"
>      run_dump_test "xsave"
>      run_dump_test "xsave-intel"
>      run_dump_test "aes"
> --- /dev/null   1970-01-01 00:00:00.000000000 +0000
> +++ 2017-11-10/gas/testsuite/gas/i386/noextreg.d        2017-11-13 17:55:34.632165025 +0100
> @@ -0,0 +1,53 @@
> +#objdump: -dw
> +#name: ix86 no extended registers
> +
> +.*:     file format .*
> +
> +Disassembly of section .text:
> +
> +0+ <ix86>:
> +[      ]*[a-f0-9]+:    c5 f9 db c0             vpand  %xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c4 c1 79 db c0          vpand  %xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c4 c1 39 db c0          vpand  %xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    62 f1 7d 08 db c0       vpandd %xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    62 d1 7d 08 db c0       vpandd %xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    62 f1 3d 08 db c0       vpandd %xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    62 f1 7d 00 db c0       vpandd %xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c4 e3 79 4c c0 00       vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c4 c3 79 4c c0 00       vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c4 e3 39 4c c0 00       vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c4 e3 79 4c c0 80       vpblendvb %xmm0,%xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    62 f2 7d 0f 90 0c 00    vpgatherdd \(%eax,%xmm0(,1)?\),%xmm1\{%k7\}
> +[      ]*[a-f0-9]+:    62 d2 7d 0f 90 0c 00    vpgatherdd \(%eax,%xmm0(,1)?\),%xmm1\{%k7\}
> +[      ]*[a-f0-9]+:    62 f2 7d 07 90 0c 00    vpgatherdd \(%eax,%xmm0(,1)?\),%xmm1\{%k7\}
> +[      ]*[a-f0-9]+:    c4 e2 78 f2 00          andn   \(%eax\),%eax,%eax
> +[      ]*[a-f0-9]+:    c4 e2 38 f2 00          andn   \(%eax\),%eax,%eax
> +[      ]*[a-f0-9]+:    c4 c2 78 f2 00          andn   \(%eax\),%eax,%eax
> +[      ]*[a-f0-9]+:    c4 e2 f8 f2 00          andn   \(%eax\),%eax,%eax
> +[      ]*[a-f0-9]+:    8f e9 78 01 20          tzmsk  \(%eax\),%eax
> +[      ]*[a-f0-9]+:    8f c9 78 01 20          tzmsk  \(%eax\),%eax
> +[      ]*[a-f0-9]+:    8f e9 38 01 20          tzmsk  \(%eax\),%eax
> +[      ]*[a-f0-9]+:    8f e9 f8 01 20          tzmsk  \(%eax\),%eax
> +[      ]*[a-f0-9]+:    8f e9 78 12 c0          llwpcb %eax
> +[      ]*[a-f0-9]+:    8f c9 78 12 c0          llwpcb %eax
> +[      ]*[a-f0-9]+:    8f e9 f8 12 c0          llwpcb %eax
> +[      ]*[a-f0-9]+:    8f e8 78 c0 c0 01       vprotb \$(0x)?1,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    8f e8 78 c0 00 01       vprotb \$(0x)?1,\(%eax\),%xmm0
> +[      ]*[a-f0-9]+:    8f e9 78 90 c0          vprotb %xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    8f e9 78 90 00          vprotb %xmm0,\(%eax\),%xmm0
> +[      ]*[a-f0-9]+:    8f e9 f8 90 00          vprotb \(%eax\),%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    8f c8 78 c0 c0 01       vprotb \$(0x)?1,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    8f c8 78 c0 00 01       vprotb \$(0x)?1,\(%eax\),%xmm0
> +[      ]*[a-f0-9]+:    8f c9 b8 90 c0          vprotb %xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    8f c9 78 90 00          vprotb %xmm0,\(%eax\),%xmm0
> +[      ]*[a-f0-9]+:    8f e9 38 90 c0          vprotb %xmm0,%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    8f c9 f8 90 00          vprotb \(%eax\),%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c4 e3 79 68 00 00       vfmaddps %xmm0,\(%eax\),%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c4 e3 39 68 00 00       vfmaddps %xmm0,\(%eax\),%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c4 e3 79 68 00 80       vfmaddps %xmm0,\(%eax\),%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c4 e3 79 68 00 0f       vfmaddps %xmm0,\(%eax\),%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c4 e3 79 48 00 00       vpermil2ps \$(0x)?0,%xmm0,\(%eax\),%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c4 e3 39 48 00 00       vpermil2ps \$(0x)?0,%xmm0,\(%eax\),%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c4 e3 79 48 00 80       vpermil2ps \$(0x)?0,%xmm0,\(%eax\),%xmm0,%xmm0
> +[      ]*[a-f0-9]+:    c3                      ret[    ]*

Where are there "(,1)?"?  Under what conditions will
assembler/disassembler generate
different outputs?


-- 
H.J.



More information about the Binutils mailing list